| Patent Number |
Title Of Patent |
Date Issued |
| 6593614 |
Integrated circuit configuration having at least one transistor and one capacitor, and method fo |
July 15, 2003 |
| A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a fir |
| 6518628 |
Integrated CMOS circuit configuration, and production of same |
February 11, 2003 |
| An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surf |
| 6475866 |
Method for production of a memory cell arrangement |
November 5, 2002 |
| A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is re |
| 6445046 |
Memory cell arrangement and process for manufacturing the same |
September 3, 2002 |
| A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate |
| 6274431 |
Method for manufacturing an integrated circuit arrangement having at least one MOS transistor |
August 14, 2001 |
| An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the cha |
| 6265748 |
Storage cell arrangement in which vertical MOS transistors have at least three different thresho |
July 24, 2001 |
| A memory cell arrangement, and method for producing same, which includes vertical MOS transistors as memory cells wherein the information is stored by means of at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is |
| 6229169 |
Memory cell configuration, method for fabricating it and methods for operating it |
May 8, 2001 |
| A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the |
| 6191459 |
Electrically programmable memory cell array, using charge carrier traps and insulation trenches |
February 20, 2001 |
| An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trench |
| 6184045 |
Method for DRAM cell arrangement and method for its production |
February 6, 2001 |
| A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis o |
| 6180979 |
Memory cell arrangement with vertical MOS transistors and the production process thereof |
January 30, 2001 |
| In a memory cell arrangement which has vertical MOS transistors as memory cells, the information is stored by different threshold voltages of the transistors. For this purpose, dopant regions are formed for an information state by angled implantation or outdiffusion in the upper regi |
| 6180458 |
Method of producing a memory cell configuration |
January 30, 2001 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 6153475 |
Method for the manufacturing a memory cell configuration |
November 28, 2000 |
| For the manufacture of a memory cell arrangement with first memory cells that comprise a vertical MOS transistor and with second memory cells that do not comprise an MOS transistor, whereby the memory cells are arranged along opposite edges of strip-type trenches, memory cells that are |
| 6147376 |
DRAM cell arrangement and method for its production |
November 14, 2000 |
| A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis o |
| 6125050 |
Configuration for driving parallel lines in a memory cell configuration |
September 26, 2000 |
| Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS |
| 6066876 |
Integrated circuit arrangement having at least one MOS transistor manufactured by use of a plana |
May 23, 2000 |
| An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the cha |
| 6064101 |
Read-only memory cell arrangement |
May 16, 2000 |
| A read-only memory cell arrangement having planar MOS transistors which are arranged in parallel rows. Neighboring rows run alternately on the bottom of longitudinal trenches and run between neighboring longitudinal trenches. Bit lines run transversely and word lines run parallel to the |
| 6049105 |
DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing |
April 11, 2000 |
| A DRAM cell arrangement having dynamic, self-amplifying memory cells, and method for manufacturing same, wherein each memory cell includes a selection transistor, a memory transistor and a diode structure. The selection transistor and the memory transistor are each fashioned as verti |
| 6040995 |
Method of operating a storage cell arrangement |
March 21, 2000 |
| For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide laye |
| 5998261 |
Method of producing a read-only storage cell arrangement |
December 7, 1999 |
| An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. |
| 5994746 |
Memory cell configuration and method for its fabrication |
November 30, 1999 |
| The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on |
| 5990536 |
Integrated circuit arrangement having at least two mutually insulated components, and method for |
November 23, 1999 |
| An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the trench. The components are in this |
| 5977589 |
DRAM cell arrangement and method for the production thereof |
November 2, 1999 |
| A memory cell containing at least three vertical transistors. A first transistor and a second transistor, or a third transistor are arranged over each other with reference to a y-axis proceeding perpendicularly to a surface of a substrate. The second transistor and the third transistor c |
| 5973373 |
Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of differe |
October 26, 1999 |
| A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement |
| 5959328 |
Electrically programmable memory cell arrangement and method for its manufacture |
September 28, 1999 |
| An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on |
| 5943572 |
Electrically writable and erasable read-only memory cell arrangement and method for its producti |
August 24, 1999 |
| An electrically writable and erasable read-only memory cell arrangement having memory cells. Each of the memory cells having an MOS transistor having a floating gate (6"). The MOS transistors are arranged in rows which run parallel. Adjacent rows run in each case alternately on the b |
| 5920778 |
Read-only memory cell arrangement and method for its production |
July 6, 1999 |
| In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). T |
| 5920099 |
Read-only memory cell array and process for manufacturing it |
July 6, 1999 |
| A read-only memory cell array has a plurality of individual memory cells which each have a MOS transistor and which are arranged in rows running in parallel. In this context, adjacent rows run alternately at the bottom of the longitudinal trenches (6) and between adjacent longitudinal tr |
| 5882969 |
Method for manufacturing an electrically writeable and erasable read-only memory cell arrangemen |
March 16, 1999 |
| In a method for manufacturing an electrically writeable and erasable ad-only memory cell arrangement, by self-adjusting process steps, a read-only memory cell arrangement having memory cells that respectively comprise an MOS transistor with a floating gate is manufactured. The MOS tr |
| 5854500 |
DRAM cell array with dynamic gain memory cells |
December 29, 1998 |
| A dynamic gain memory cell of a DRAM cell array includes a planar MOS transistor as a selection transistor and a vertical MOS transistor as a memory transistor, which are connected to one another via a common source/drain region. The memory transistor has a gate electrode of doped si |
| 5821591 |
High density read only memory cell configuration and method for its production |
October 13, 1998 |
| A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed |
| 5817552 |
Process of making a dram cell arrangement |
October 6, 1998 |
| For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of whi |
| 5744393 |
Method for production of a read-only-memory cell arrangement having vertical MOS transistors |
April 28, 1998 |
| A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS t |
| 5736761 |
DRAM cell arrangement and method for its manufacture |
April 7, 1998 |
| The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capa |
| 5710072 |
Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cel |
January 20, 1998 |
| To produce an arrangement containing self-amplifying dynamic MOS transistor memory cells which each comprise a selection transistor, a memory transistor and a diode structure, the selection transistor and the memory transistor being connected in series via a common nodal point and the |
