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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kojima; Hiromi
Address:
Chiba, JP
No. of patents:
1
Patents:












Patent Number Title Of Patent Date Issued
8006156 Method of generating test condition for detecting delay faults in semiconductor integrated circu August 23, 2011
Various exemplary embodiments provide methods and apparatuses for generating test conditions that efficiently detect delay faults while preventing overkill. According to an exemplary embodiment, i) test timing correcting block sets test timing faster than the actual operation timing










 
 
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