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Inventor:
Ko; Jeng-Dar
Address:
Pade, TW
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
8587091 Wafer-leveled chip packaging structure and method thereof November 19, 2013
A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the firs
7838333 Electronic device package and method of manufacturing the same November 23, 2010
The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are
7632707 Electronic device package and method of manufacturing the same December 15, 2009
The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are
7528009 Wafer-leveled chip packaging structure and method thereof May 5, 2009
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating la
7294920 Wafer-leveled chip packaging structure and method thereof November 13, 2007
This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating la










 
 
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