| Patent Number |
Title Of Patent |
Date Issued |
| 7369562 |
Method and apparatus for forwarding of telecommunications traffic |
May 6, 2008 |
| The present invention relates to a telecommunications node (1a) that is able to handle IP-traffic and to terminate telecommunications traffic, which node includes means for simple and effective load distribution between resources (40-43) in the node. The inventive telecommunications |
| 7197622 |
Efficient mapping of signal elements to a limited range of identifiers |
March 27, 2007 |
| Signal elements are mapped to a limited range of identifiers by emulating a "virtual" space of identifiers larger than the real limited space of identifiers. The larger virtual identifier space is implemented by an intermediate memory, which provides storage of identifiers assigned from |
| 6662203 |
Batch-wise handling of signals in a processing system |
December 9, 2003 |
| The present invention relates to multiprocessing systems in which signals or processes are scheduled in order of their priority level. The invention is based on batch-wise acceptance and scheduling of job signals, and utilizes at least one delay queue for temporarily storing job signals |
| 6438748 |
Apparatus and method for conversion of messages |
August 20, 2002 |
| To achieve a highly efficient upgrade of software in computer based systems a message conversion apparatus (34) comprises an interface unit (36) for message conversion information (MCI) describing at least one message being exchanged in a software processing system before and after an up |
| 6415279 |
Method and access means for determining the storage address of a data value in a memory device |
July 2, 2002 |
| A method and an access mechanism for determining the storage address of a predetermined data value (D.sub.1, D.sub.2, D.sub.3) in a memory device is disclosed. The data values are stored in an increasing order sequentially in a column direction according to a binary tree data structure. |
| 6347396 |
Disturbance free update of data |
February 12, 2002 |
| To improve the efficiency for an update process in a software processing device with a plurality of memory partitions (4,14) it is proposed to continue the execution of old software on original data stored in a first memory partition (4). In case the same state for data of old and new |
| 6259620 |
Multiple entry matching in a content addressable memory |
July 10, 2001 |
| A content addressable memory (CAM) permits a matching operation to be performed over multiple stored entries. The CAM includes a matrix of cells having (n+1) columns and m rows, wherein n and m are each integers greater than or equal to 1, and wherein each row of cells comprises: n data |
| 6223304 |
Synchronization of processors in a fault tolerant multi-processor system |
April 24, 2001 |
| A method and system are described for synchronizing a first processor unit with a second processor unit in a fault tolerant system comprising a plurality of processing units where all processing units are executing the same processes in synchronization. The invention is readily adapted t |
| 4985826 |
Method and device to execute two instruction sequences in an order determined in advance |
January 15, 1991 |
| A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not guaranteed to be independent of data information used in the first sequence. Increased data |
| 4956770 |
Method and device to execute two instruction sequences in an order determined in advance |
September 11, 1990 |
| A data processing system which executes two instruction sequences in an order determined in advance. With the aid of instructions, a main memory common to both sequences is activated for data information reading/writing. Increased data handling capacity is achieved in the following m |
| 4791563 |
Arrangement for apportioning priority among co-operating computers |
December 13, 1988 |
| A priority apportioning arrangement for computers with processors of two types, namely a first high-priority type which can determine its priority itself in relation to processors of a second low-priority type when using a common bus. The arrangement contains a first logic circuit (20) w |
