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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kirby; Kyle K.
Address:
Boise, ID
No. of patents:
91
Patents:


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Patent Number Title Of Patent Date Issued
8294273 Methods for fabricating and filling conductive vias and conductive vias so formed October 23, 2012
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching
8084866 Microelectronic devices and methods for filling vias in microelectronic devices December 27, 2011
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending th
8053857 Packaged microelectronic imagers and methods of packaging microelectronic imagers November 8, 2011
Methods for forming electrically conductive through-wafer interconnects in microelectronic devices and microelectronic devices are disclosed herein. In one embodiment, a microelectronic device can include a monolithic microelectronic substrate with an integrated circuit has a front s
8035179 Packaged microelectronic imagers and methods of packaging microelectronic imagers October 11, 2011
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrat
7993944 Microelectronic imagers with optical devices having integral reference features and methods for August 9, 2011
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and
7960829 Support structure for use in thinning semiconductor substrates and for supporting thinned semico June 14, 2011
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to
7918383 Methods for placing substrates in contact with molten solder April 5, 2011
Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing
7892972 Methods for fabricating and filling conductive vias and conductive vias so formed February 22, 2011
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching
7858429 Packaged microelectronic imagers and methods of packaging microelectronic imagers December 28, 2010
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrat
7855140 Method of forming vias in semiconductor substrates and resulting structures December 21, 2010
Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the cond
7791184 Image sensor packages and frame structure thereof September 7, 2010
A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment.
7759800 Microelectronics devices, having vias, and packaged microelectronic devices having vias July 20, 2010
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the
7713841 Methods for thinning semiconductor substrates that employ support structures formed on the subst May 11, 2010
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to
7709776 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i May 4, 2010
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7701039 Semiconductor devices and in-process semiconductor devices having conductor filled vias April 20, 2010
At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an ele
7649145 Compliant spring contact structures January 19, 2010
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrat
7648900 Vias having varying diameters and fills for use with a semiconductor device and methods of formi January 19, 2010
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening.
7645635 Frame structure and semiconductor attach process for use therewith for fabrication of image sens January 12, 2010
A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed i
7598167 Method of forming vias in semiconductor substrates without damaging active regions thereof and r October 6, 2009
Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate unde
7589008 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces f September 15, 2009
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having a plurality of microelectronic d
7547850 Semiconductor device assemblies with compliant spring contact structures June 16, 2009
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a silicon wafer or a carrier substrate is provided. At least one layer of a metal or alloy film may be deposited on the substrat
7528491 Semiconductor components and assemblies including vias of varying lateral dimensions May 5, 2009
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third openin
7504615 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic i March 17, 2009
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external
7498675 Semiconductor component having plate, stacked dice and conductive vias March 3, 2009
A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back sid
7498647 Packaged microelectronic imagers and methods of packaging microelectronic imagers March 3, 2009
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrat
7495316 Methods of forming conductive vias and methods of forming multichip modules including such condu February 24, 2009
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hol
7488899 Compliant contact pin assembly and card system February 10, 2009
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension
7459393 Method for fabricating semiconductor components with thinned substrate, circuit side contacts, c December 2, 2008
A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening from a backside of the substrate to the contact, forming a conductive via in the opening in electrical contact with a surface of t
7456639 Compliant contact structure November 25, 2008
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least
7452743 Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the November 18, 2008
Microelectronic imaging units and methods for manufacturing a plurality of imaging units at the wafer level are disclosed herein. In one embodiment, a method for manufacturing a plurality of imaging units includes providing an imager workpiece having a plurality of imaging dies inclu
7449910 Test system for semiconductor components having conductive spring contacts November 11, 2008
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc
7429494 Microelectronic imagers with optical devices having integral reference features and methods for September 30, 2008
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and
7425499 Methods for forming interconnects in vias and microelectronic workpieces including such intercon September 16, 2008
Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece
7419841 Microelectronic imagers and methods of packaging microelectronic imagers September 2, 2008
Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electricall
7411304 Semiconductor interconnect having conductive spring contacts August 12, 2008
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc
7410898 Methods of fabricating interconnects for semiconductor components August 12, 2008
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an opening is formed which extends entirely through the substrate. A first material is deposited along sidewalls of the opening a
7409762 Method for fabricating an interconnect for semiconductor components August 12, 2008
A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flex
7394267 Compliant contact pin assembly and card system July 1, 2008
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension
7391117 Method for fabricating semiconductor components with conductive spring contacts June 24, 2008
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conduc
7389581 Method of forming compliant contact structures June 24, 2008
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least
7385412 Systems and methods for testing microfeature devices June 10, 2008
Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual
7378342 Methods for forming vias varying lateral dimensions May 27, 2008
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third openin
7364985 Method for creating electrical pathways for semiconductor device structures using laser machinin April 29, 2008
A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention includes providing a semiconductor substrate and forming one or more depressions in the semiconductor substrate using laser m
7363694 Method of testing using compliant contact structures, contactor cards and test system April 29, 2008
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a compliant contact formed therein. The compliant contact structure includes a portion fixed within the substrate and at least
7358751 Contact pin assembly and contactor card April 15, 2008
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension
7355267 Substrate, semiconductor die, multichip module, and system including a via structure comprising April 8, 2008
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hol
7354863 Methods of selectively removing silicon April 8, 2008
An etch solution that comprises tetramethylammonium hydroxide ("TMAH") and at least one organic solvent. The etch solution may be substantially free of water. The etch solution is formulated to selectively etch a silicon layer relative to other layers on an integrated circuit. The TMAH m
7348671 Vias having varying diameters and fills for use with a semiconductor device and methods of formi March 25, 2008
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than the second opening.
7332413 Semiconductor wafers including one or more reinforcement structures and methods of forming the s February 19, 2008
Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned region of the wafer. One or more reinforcement structures may be defined on the wafer. Semiconductor wafers include one or
7329943 Microelectronic devices and methods for forming interconnects in microelectronic devices February 12, 2008
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate
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