| Patent Number |
Title Of Patent |
Date Issued |
| 8198702 |
Electrical fuse device |
June 12, 2012 |
| The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current de |
| 8198701 |
Semiconductor device having thermally formed air gap in wiring layer and method of fabricating s |
June 12, 2012 |
| A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width a |
| 8013420 |
Electrical fuse device |
September 6, 2011 |
| The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current de |
| 7892966 |
Semiconductor device having thermally formed air gap in wiring layer and method of fabricating s |
February 22, 2011 |
| A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width a |
| 7638423 |
Semiconductor device and method of forming wires of semiconductor device |
December 29, 2009 |
| A method of forming wires of a semiconductor device including forming a first metal wire on a semiconductor substrate; forming a first insulating film on the first metal wire; etching a portion of the first insulating film to expose a surface portion of the first metal wire; forming a fi |
| 7446033 |
Method of forming a metal interconnection of a semiconductor device, and metal interconnection f |
November 4, 2008 |
| A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal |
