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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Khosla; Mukul
Address:
San Jose, CA
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
6726824 Closed loop monitoring of electroplating bath constituents using mass spectrometry April 27, 2004
The present invention provides methods and apparatus for analysis and monitoring of electrolyte bath composition. Based on the results of the analysis, the invention controls electrolyte bath composition and plating hardware. Thus, the invention provides control of electroplating process
6667474 Capillary tube assembly with replaceable capillary tube December 23, 2003
The present invention relates to a heated capillary assembly which connects an atmospheric pressure ionization source to a lower pressure mass analyzing system which comprises a capillary tube removably secured to, and extending through the bore of a capillary support assembly.
6554914 Passivation of copper in dual damascene metalization April 29, 2003
The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while
6497734 Apparatus and method for enhanced degassing of semiconductor wafers for increased throughput December 24, 2002
A multi-level shelf degas station relying on at least two heaters integrated within wafer holding shelves or slots, where the semiconductor wafers do not have direct contact with the heater shelves. The heaters provide conduction heating. In order to degas a wafer, the heater and waf
6441370 Linear multipole rod assembly for mass spectrometers August 27, 2002
A multiple-pole electrode assembly is disclosed for use in mass spectrometers or other applications such as ion traps or ion guides. The disclosed apparatus provides a rod mounting and connection assembly in which equally spaced rectangular rods are embedded in spaced, dimensionally
6319842 Method of cleansing vias in semiconductor wafer having metal conductive layer November 20, 2001
Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semicondu










 
 
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