| Patent Number |
Title Of Patent |
Date Issued |
| 7220985 |
Self aligned memory element and wordline |
May 22, 2007 |
| An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top |
| 7005386 |
Method for reducing resist height erosion in a gate etch process |
February 28, 2006 |
| According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coat |
| 6962849 |
Hard mask spacer for sublithographic bitline |
November 8, 2005 |
| A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6828259 |
Enhanced transistor gate using E-beam radiation |
December 7, 2004 |
| A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6455333 |
Method of achieving stable deep ultraviolet (DUV) resist etch rate for gate critical dimension ( |
September 24, 2002 |
| A method of stabilizing the DUV resist etch rate for a gate critical dimension, especially for a CD.ltoreq.75 .mu.m. More specifically, the present invention provides a method for stabilizing a deep ultraviolet (DUV) resist etch rate by utilizing the directly proportionate relationsh |
