| Patent Number |
Title Of Patent |
Date Issued |
| 7601575 |
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor per |
October 13, 2009 |
| The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active d |
| 7560792 |
Reliable high voltage gate dielectric layers using a dual nitridation process |
July 14, 2009 |
| Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) |
| 7553718 |
Methods, systems and structures for forming semiconductor structures incorporating high-temperat |
June 30, 2009 |
| A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embod |
| 7535066 |
Gate structure and method |
May 19, 2009 |
| A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition. |
| 7514308 |
CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gat |
April 7, 2009 |
| The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semicon |
| 7402524 |
Post high voltage gate oxide pattern high-vacuum outgas surface treatment |
July 22, 2008 |
| The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate diele |
| 7345001 |
Gate dielectric having a flat nitrogen profile and method of manufacture therefor |
March 18, 2008 |
| The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes form |
| 7339240 |
Dual-gate integrated circuit semiconductor device |
March 4, 2008 |
| The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate diele |
| 7227201 |
CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gat |
June 5, 2007 |
| The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semicon |
| 7226834 |
PMD liner nitride films and fabrication methods for improved NMOS performance |
June 5, 2007 |
| Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the |
| 7217626 |
Transistor fabrication methods using dual sidewall spacers |
May 15, 2007 |
| Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of |
| 7192894 |
High performance CMOS transistors using PMD liner stress |
March 20, 2007 |
| A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting |
| 7183165 |
Reliable high voltage gate dielectric layers using a dual nitridation process |
February 27, 2007 |
| Dual gate dielectric layers are formed on a semiconductor substrate for MOS transistor fabrication. A first dielectric layer (30) is formed on a semiconductor substrate (10). A first plasma nitridation process is performed on said first dielectric layer. The first dielectric layer (30) |
| 7129127 |
Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation |
October 31, 2006 |
| A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown |
| 7049242 |
Post high voltage gate dielectric pattern plasma surface treatment |
May 23, 2006 |
| The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate diele |
| 7018925 |
Post high voltage gate oxide pattern high-vacuum outgas surface treatment |
March 28, 2006 |
| The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate diele |
| 7012028 |
Transistor fabrication methods using reduced width sidewall spacers |
March 14, 2006 |
| Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by |
| 6930007 |
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor per |
August 16, 2005 |
| The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopan |
| 6869862 |
Method for improving a physical property defect value of a gate dielectric |
March 22, 2005 |
| The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property |
| 6780719 |
Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures |
August 24, 2004 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer |
| 6730566 |
Method for non-thermally nitrided gate formation for high voltage devices |
May 4, 2004 |
| A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introdu |
| 6632747 |
Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile |
October 14, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to c |
| 6610614 |
Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates |
August 26, 2003 |
| A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform |
| 6548366 |
Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile |
April 15, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer |
| 6503846 |
Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor g |
January 7, 2003 |
| An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer |
