| Patent Number |
Title Of Patent |
Date Issued |
| 7613813 |
Method and apparatus for reducing host overhead in a socket server implementation |
November 3, 2009 |
| A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the netwo |
| 7606998 |
Store instruction ordering for multi-core processor |
October 20, 2009 |
| A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue. |
| 7594081 |
Direct access to low-latency memory |
September 22, 2009 |
| A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache co |
| 7558925 |
Selective replication of data structures |
July 7, 2009 |
| Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure |
| 7535907 |
TCP engine |
May 19, 2009 |
| A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs |
| 7398386 |
Transparent IPSec processing inline between a framer and a network component |
July 8, 2008 |
| A method and apparatus for transparent processing of IPsec network traffic by a security processor in line between a framer and a network processor. Security processor parses packet header and tail information to determine if encryption or decryption is required. After encryption or decr |
| 7305567 |
Decoupled architecture for data ciphering operations |
December 4, 2007 |
| In one embodiment, an apparatus comprises a microcontroller unit to store instructions into an execution queue. The apparatus also comprises an execution queue unit to generate a widely decoded functional execution instruction based on at least one instruction stored in the execution |
| 7240203 |
Method and apparatus for establishing secure sessions |
July 3, 2007 |
| A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a |
| 7213087 |
Mechanism to control the allocation of an N-source shared buffer |
May 1, 2007 |
| A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit an |
| 7209531 |
Apparatus and method for data deskew |
April 24, 2007 |
| A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align t |
| 7152191 |
Fault containment and error recovery in a scalable multiprocessor |
December 19, 2006 |
| A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a fa |
| 7100096 |
Special encoding of known bad data |
August 29, 2006 |
| A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the |
| 7099913 |
Speculative directory writes in a directory based cache coherent nonuniform memory access protoc |
August 29, 2006 |
| A system and method is disclosed that reduces the latency of directory updates in a directory based Distributed Shared Memory computer system by speculating the next directory state. The distributed multiprocessing computer system contains a number of processor nodes each connected to |
| 7076597 |
Broadcast invalidate scheme |
July 11, 2006 |
| A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to proces |
| 7031869 |
Method and apparatus for managing timestamps when storing data |
April 18, 2006 |
| A system is disclosed in which an on-chip logic analyzer (OCLA) includes timestamp logic capable of providing clock cycle resolution of data entries using a relatively small number of bits. The timestamp logic includes a counter that is reset each time a store operation occurs. The c |
| 7024533 |
Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic init |
April 4, 2006 |
| A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory |
| 6961781 |
Priority rules for reducing network message routing latency |
November 1, 2005 |
| A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance |
| 6920512 |
Computer architecture and system for efficient management of bi-directional bus |
July 19, 2005 |
| An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be red |
| 6918015 |
Scalable directory based cache coherence protocol |
July 12, 2005 |
| A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the |
| 6789147 |
Interface for a security coprocessor |
September 7, 2004 |
| A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a |
| 6754739 |
Computer resource management and allocation system |
June 22, 2004 |
| A method and architecture for improved system resource management and allocation for the processing of request and response messages in a computer system. The resource management scheme provides for dynamically sharing system resources, such as data buffers, between request and respo |
| 6751721 |
Broadcast invalidate scheme |
June 15, 2004 |
| A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to proces |
| 6738836 |
Scalable efficient I/O port protocol |
May 18, 2004 |
| A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or mor |
| 6715057 |
Efficient translation lookaside buffer miss processing in computer systems with a large range of |
March 30, 2004 |
| A system and method is disclosed to efficiently translate virtual-to-physical addresses of large size pages of data by eliminating one level of a multilevel page table. A computer system containing a processor includes a translation lookaside buffer ("TLB") in the processor. The proc |
| 6704817 |
Computer architecture and system for efficient management of bi-directional bus |
March 9, 2004 |
| An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular by intelligently managing reads and writes on a bi-directional bus, bus latency can be redu |
| 6691207 |
Method and apparatus for implementing loop compression in a program counter trace |
February 10, 2004 |
| A system is disclosed in which an on-chip logic analyzer (OCLA) includes a loop detector logic which receives incoming program counter (PC) data and detects when software loops exist. When a software loop is detected, the loop detector may be configured to store the first loop in memory, |
| 6681295 |
Fast lane prefetching |
January 20, 2004 |
| A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded i |
| 6678840 |
Fault containment and error recovery in a scalable multiprocessor |
January 13, 2004 |
| A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failur |
| 6668335 |
System for recovering data in a multiprocessor system comprising a conduction path for each bit |
December 23, 2003 |
| A system comprising a communications link between processors configured to transmit packets between transmitting and receiving processors. The communications link comprises a conduction path for each bit in the packet and the paths are grouped into separate bundles and routed along diffe |
| 6662319 |
Special encoding of known bad data |
December 9, 2003 |
| A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the me |
| 6662265 |
Mechanism to track all open pages in a DRAM memory system |
December 9, 2003 |
| A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to stor |
| 6654858 |
Method for reducing directory writes and latency in a high performance, directory-based, coheren |
November 25, 2003 |
| A computer system has a plurality of processors wherein each processor preferably has its own cache memory. Each processor or group of processors may have a memory controller that interfaces to a main memory. Each main memory includes a "directory" that maintains the directory coherence |
| 6651144 |
Method and apparatus for developing multiprocessor cache control protocols using an external ack |
November 18, 2003 |
| A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a |
| 6636955 |
Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic init |
October 21, 2003 |
| A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory |
| 6633960 |
Scalable directory based cache coherence protocol |
October 14, 2003 |
| A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the |
| 6622225 |
System for minimizing memory bank conflicts in a computer system |
September 16, 2003 |
| A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to |
| 6567900 |
Efficient address interleaving with simultaneous multiple locality options |
May 20, 2003 |
| A computer system includes multiple processors, each of which includes an associated memory. Each of the processors is capable of accessing the memory of all other processors. Memory can be stored and accessed using different addressing schemes. For data that will only be used by the loc |
| 6546453 |
Proprammable DRAM address mapping mechanism |
April 8, 2003 |
| A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor ad |
| 6493802 |
Method and apparatus for performing speculative memory fills into a microprocessor |
December 10, 2002 |
| According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more |
| 6397302 |
Method and apparatus for developing multiprocessor cache control protocols by presenting a clean |
May 28, 2002 |
| A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiproc |
| 6349366 |
Method and apparatus for developing multiprocessor cache control protocols using a memory manage |
February 19, 2002 |
| A memory management system couples processors to each other and to a main memory. Each processor may have one or more associated caches local to that processor. A system port of the memory management system receives a request from a source processor of the processors to access a block of |
| 6314496 |
Method and apparatus for developing multiprocessor cache control protocols using atomic probe co |
November 6, 2001 |
| A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a n |
| 6295583 |
Method and apparatus for resolving probes in multi-processor systems which do not use external d |
September 25, 2001 |
| A processor of a multiprocessor system is configured to transmit a full probe to a cache associated with the processor to transfer data from the stored data of the cache. The data corresponding to the full probe is transferred during a time period. A first tag-only probe is also tran |
| 6253285 |
Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset |
June 26, 2001 |
| A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The |
| 6216174 |
System and method for fast barrier synchronization |
April 10, 2001 |
| Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state ("barrier_bit") is added to each processor to support a barrier. The input and output signal are couple |
| 6199153 |
Method and apparatus for minimizing pincount needed by external memory control chip for multipro |
March 6, 2001 |
| A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to trans |
| 6163821 |
Method and apparatus for balancing load vs. store access to a primary data cache |
December 19, 2000 |
| A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when the |
