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Inventor:
Keshtbod; Parviz
Address:
Los Altos, CA
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
8148174 Magnetic tunnel junction (MTJ) formation with two-step process April 3, 2012
A method of manufacturing a magnetic memory element includes the steps of performing a first etching an oxide layer is etched, using a first photo-resist, the oxide layer formed on top of a contact layer that is formed on top of a magneto tunnel junction (MTJ), depositing a second ph
6587382 Nonvolatile memory using flexible erasing methods and method and system for using same July 1, 2003
An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each b
6411546 Nonvolatile memory using flexible erasing methods and method and system for using same June 25, 2002
An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each b
4608585 Electrically erasable PROM cell August 26, 1986
In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise
4527255 Non-volatile static random-access memory cell July 2, 1985
A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The varia










 
 
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