| Patent Number |
Title Of Patent |
Date Issued |
| RE33972 |
Two square memory cells |
June 23, 1992 |
| A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the |
| 5719080 |
Semiconductor trench capacitor cell having a buried strap |
February 17, 1998 |
| A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the t |
| 5710057 |
SOI fabrication method |
January 20, 1998 |
| A first region of a seed substrate is separated from a bonded handle substrate by etching and/or fracturing a second region of the seed substrate. A third region of the seed substrate remains bonded to the handle wafer. Etching and etch ant distribution are facilitated by capillary a |
| 5684314 |
Trench capacitor precharge structure and leakage shield |
November 4, 1997 |
| An integrated structure is provided that includes a DRAM cell with a trench storage capacitor, and a corresponding storage node precharge circuit. The entire structure ideally requires only eight square features of area per memory bit. The structure also provides a partial leakage curren |
| 5684313 |
Vertical precharge structure for DRAM |
November 4, 1997 |
| A DRAM one device cell and an associated precharge circuit are integrated together in a novel structure having an area of only four square features. The structure also provides physical and electrical separation between adjacent cells along a direction parallel to the DRAM word lines. Th |
| 5635419 |
Porous silicon trench and capacitor structures |
June 3, 1997 |
| The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porou |
| 5583368 |
Stacked devices |
December 10, 1996 |
| Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and conta |
| 5576566 |
Semiconductor trench capacitor cell having a buried strap |
November 19, 1996 |
| A semiconductor trench capacitor structure having a first level aligned isolation structure and buried strap that extends from within the trench into the doped semiconductor substrate. The semiconductor trench capacitor structure may be fabricated by forming a shallow trench within the t |
| 5532965 |
Memory precharge scheme using spare column |
July 2, 1996 |
| Performance is improved for a memory array composed of storage elements which require a preconditioning operation prior to writing new data or rewriting old data. At least one spare column of memory elements is provided. The spare column is preconditioned during a time when it is not |
| 5521118 |
Sidewall strap |
May 28, 1996 |
| The present invention is a sidewall connector providing a conductive path linking at least two conductive regions. The sidewall connector has a top portion comprising an outer surface. A conductive member contacts the top portion, connecting the rail to a conductive region or to an exter |
| 5508542 |
Porous silicon trench and capacitor structures |
April 16, 1996 |
| The invention provides a capacitor structure utilizing porous silicon as a first plate of the capacitor structure, thereby greatly increasing the surface area available for the capacitor and thereby the capacitance attainable. The invention also provides a trench structure having a porou |
| 5466636 |
Method of forming borderless contacts using a removable mandrel |
November 14, 1995 |
| A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is ma |
| 5466636 |
Method of forming borderless contacts using a removable mandrel |
November 14, 1995 |
| A semiconductor fabrication process for forming borderless contacts (130, 170, 172) using a removable mandrel (110). The process involves depositing a mandrel on an underlying barrier layer (100) designed to protect underlying structures (40) formed on a substrate (24). The mandrel is ma |
| 5466626 |
Micro mask comprising agglomerated material |
November 14, 1995 |
| The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface |
| 5466626 |
Micro mask comprising agglomerated material |
November 14, 1995 |
| The subject invention provides a method of forming recesses in a substrate such as a capacitor so as to increase the surface area thereof and therefore the charge storage capacity of the capacitor. This is accomplished by utilizing a micro mask formed by agglomeration on the surface |
| 5414656 |
Low charge consumption memory |
May 9, 1995 |
| A dynamic random access memory is improved by a storage node precharge circuit so as to obtain both high stored voltage level and low charge consumption from a power supply. High voltage levels are written via the precharge circuit. Subsequently, low voltage levels are written via the |
| 5412246 |
Low temperature plasma oxidation process |
May 2, 1995 |
| A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of |
| 5399516 |
Method of making shadow RAM cell having a shallow trench EEPROM |
March 21, 1995 |
| A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow |
| 5384281 |
Non-conformal and oxidizable etch stops for submicron features |
January 24, 1995 |
| A process for etching narrow features, particularly submicron borderless contacts, in a semiconductor substrate is disclosed. The process comprises depositing, by an orientation-sensitive technique, film which will act as an etch stop. The film is significantly thicker on horizontal surf |
| 5365097 |
Vertical epitaxial SOI transistor, memory cell and fabrication methods |
November 15, 1994 |
| Vertical epitaxial SOI transistors and memory cells are disclosed. The devices are formed completely within a substrate trench and have a bulk channel epitaxially grown on an exposed surface of the substrate within the trench. The bulk channel is disposed proximate to a transistor gate |
| 5360758 |
Self-aligned buried strap for trench type DRAM cells |
November 1, 1994 |
| A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to over |
| 5348905 |
Method of making diffused buried plate trench DRAM cell array |
September 20, 1994 |
| A high density substrate plate DRAM cell memory device and process are described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The |
| 5330935 |
Low temperature plasma oxidation process |
July 19, 1994 |
| A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of |
| 5264716 |
Diffused buried plate trench dram cell array |
November 23, 1993 |
| A high density substrate plate DRAM cell memory device is described in which a buried plate region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried regio |
| 5254503 |
Process of making and using micro mask |
October 19, 1993 |
| A method is provided to enable the formation of sub-lithographic relief images to increase the surface area of semiconductor structures for use in the storage nodes of DRAM cells. The method includes the steps of forming in situ a non-planar region having a relief pattern comprising sub- |
| 5196722 |
Shadow ram cell having a shallow trench eeprom |
March 23, 1993 |
| A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow |
| 5001525 |
Two square memory cells having highly conductive word lines |
March 19, 1991 |
| A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, a storage capacitor having a storage node disposed within a given sidewall of the |
| 4970689 |
Charge amplifying trench memory cell |
November 13, 1990 |
| A gain memory cell circuit includes a storage capacitor connected between a storage node and ground, a write word line, a read word line, a second capacitor capactively coupling the read word line to the storage node, a read transistor having its source/drain path coupled between the bit |
| 4939567 |
Trench interconnect for CMOS diffusion regions |
July 3, 1990 |
| A sub-surface interconnection structure for coupling an n-type diffusion to a p-type diffusion. The structure is a conductor-filled trench disposed between the diffusion regions. The trench has a thin dielectric layer on its sidewalls and bottom. The conductor within the trench contacts |
| 4914740 |
Charge amplifying trench memory cell |
April 3, 1990 |
| A charge amplifying memory cell and its memory of making based on trench technology. A trench is formed which reaches through an n-type well region to a p.sup.+ -type substrate. A triple layer is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a |
| 4838991 |
Process for defining organic sidewall structures |
June 13, 1989 |
| A conformal organic layer is used to define spacers on the sidewalls of an organic mandrel. The organic layer (e.g., parylene) can be deposited at low temperatures, and as such is compatible with temperature-sensitive mandrel materials that reflow at high deposition temperatures. The |
| 4833094 |
Method of making a dynamic ram cell having shared trench storage capacitor with sidewall-defined |
May 23, 1989 |
| A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the dop |
| 4801988 |
Semiconductor trench capacitor cell with merged isolation and node trench construction |
January 31, 1989 |
| A semiconductor trench capacitor construction having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer formed along the upper portion of the trench side walls. The trench isolation structure facilitates lar |
| 4785337 |
Dynamic ram cell having shared trench storage capacitor with sidewall-defined bridge contacts an |
November 15, 1988 |
| A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the dop |
| 4769786 |
Two square memory cells |
September 6, 1988 |
| A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the |
| 4751558 |
High density memory with field shield |
June 14, 1988 |
| A memory cell formed in a groove or trench in a semiconductor substrate is provided which includes a storage capacitor located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line disposed at the surface of the semiconductor substrate adjacent to the |
| 4648073 |
Sequential shared access lines memory cells |
March 3, 1987 |
| A memory array is provided which includes a common sense line to which is connected first and second series of cells, each cell of each series includes a storage capacitor, a switching device and a bit line connected to a plate of the storage capacitor, with a common word line connected |
| 4642491 |
Single transistor driver circuit |
February 10, 1987 |
| A driver circuit is provided which includes a field effect transistor having first and second spaced apart semiconductor regions of a given conductivity type and a third semiconductor region of a conductivity type opposite to the given conductivity type interposed between the first and |
| 4511911 |
Dense dynamic memory cell structure and process |
April 16, 1985 |
| A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense line connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a th |
| 4364074 |
V-MOS Device with self-aligned multiple electrodes |
December 14, 1982 |
| High density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal proc |
| 4326332 |
Method of making a high density V-MOS memory array |
April 27, 1982 |
| A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the |
| 4295924 |
Method for providing self-aligned conductor in a V-groove device |
October 20, 1981 |
| A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of V-groove devices, providing a conductive layer over the surface and then applying a layer of |
