| Patent Number |
Title Of Patent |
Date Issued |
| RE38428 |
Bus transaction reordering in a computer system having unordered slaves |
February 10, 2004 |
| A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment, both masters and slaves are ordered, simplifying implementation. In another embodiment, the |
| 7320048 |
Apparatus and method to switch a FIFO between strobe sources |
January 15, 2008 |
| A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data |
| 7296174 |
Apparatus and method to interface two different clock domains |
November 13, 2007 |
| A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain has a faster clock speed than the other. The gearbox is disposed between the two clock do |
| 7206110 |
Memory cell dual protection |
April 17, 2007 |
| A spatial light modulator for use in projection display applications is provided. The spatial light modulator includes a substrate including a plurality of electrically active circuits and an electrode layer electrically coupled to at least one of the plurality of electrically active |
| 7117292 |
Apparatus and method to switch a FIFO between strobe sources |
October 3, 2006 |
| A first-in, first-out (FIFO) unit switches between strobe sources. The FIFO uses a multiplexer to switch between two or more strobes so that different data strobes may be used with the FIFO to strobe in the data. In one implementation, the FIFO uses four data latches to strobe in data |
| 6941440 |
Addressing scheme supporting variable local addressing and variable global addressing |
September 6, 2005 |
| A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are i |
