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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kawai; Hiroji
Address:
Kanagawa, JP
No. of patents:
29
Patents:




Patent Number Title Of Patent Date Issued
RE38613 Method for growing a nitride compound semiconductor October 5, 2004
A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment,
6903392 Semiconductor device and its manufacturing method June 7, 2005
A semiconductor device having a single-crystal substrate made of a material different from nitride III-V compound semiconductors, and a device made on one major surface of said single-crystal substrate by using III-V compound semiconductors, including electrical connection to said device
6750481 Semiconductor laminated substrate, semiconductor crystal substrate and semiconductor device and June 15, 2004
A semiconductor crystal layer composed of GaN is grown on a base substrate composed of sapphire sandwiching a separating layer composed of AlN and a buffer layer composed of GaN. The separating layers and the buffer layers are distributed in the form of lines, and a flow-through hole for
6501154 Semiconductor substrate made of a nitride III-V compound semiconductor having a wurtzite-structu December 31, 2002
There are provided a semiconductor substrate and a semiconductor laser using the semiconductor substrate which promises smooth and optically excellent cleaved surfaces and is suitable for fabricating semiconductor lasers using nitride III-V compound semiconductors. Using a semiconductor
6468902 Semiconductor device and its manufacturing method October 22, 2002
After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive
6426264 Method of manufacturing a semiconductor laminated substrate, semiconductor crystal substrate and July 30, 2002
A semiconductor crystal layer composed of GaN is grown on a base substrate composed of sapphire sandwiching a separating layer composed of AlN and a buffer layer composed of GaN. The separating layers and the buffer layers are distributed in the form of lines, and a flow-through hole for
6413312 Method for growing a nitride compound semiconductor July 2, 2002
A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment,
6362016 Semiconductor light emitting device March 26, 2002
A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-la
6281032 Manufacturing method for nitride III-V compound semiconductor device using bonding August 28, 2001
In a semiconductor device manufacturing method capable of manufacturing semiconductor lasers, light emitting diodes or electron transport devices using nitride III-V compound semiconductors with a high productivity, a GaN semiconductor laser wafer is prepared in which a plurality of
6239033 Manufacturing method of semiconductor device May 29, 2001
After making a GaN FET by growing GaN semiconductor layers on the surface of a sapphire substrate, the bottom surface of the sapphire substrate is processed by lapping, using an abrasive liquid containing a diamond granular abrasive material and reducing the grain size of the abrasive
6235617 Semiconductor device and its manufacturing method May 22, 2001
It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation.
6140169 Method for manufacturing field effect transistor October 31, 2000
A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source
6121636 Semiconductor light emitting device September 19, 2000
A semiconductor light emitting device is provided, which does not deteriorate in luminance, maintains a high reliability, permits more free choice of an adhesive, and promises effective extraction of light to the exterior even when it is bonded to a lead frame or other support with the
6111273 Semiconductor device and its manufacturing method August 29, 2000
It is intended to provide a semiconductor device and its manufacturing method in which a high-resistance region maintaining a high resistance even under high temperatures can be made in a nitride III-V compound semiconductor layer having an electric conductivity by ion implantation.
6107162 Method for manufacture of cleaved light emitting semiconductor device August 22, 2000
A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the s
6081001 Nitride semiconductor light emitting device June 27, 2000
A luminous intensity of a semiconductor light emitting device having a multi-layer structure formed of nitride group III-V compound semiconductors is improved by having a thickness d of a light emitting layer (active layer) of the semiconductor light emitting device having a multi-la
6064082 Heterojunction field effect transistor May 16, 2000
A heterojunction field effect transistor realizing a high performance by a significant decrease. in source resistance while maintaining a sufficiently high gate resistivity to voltage is provided. Sequentially stacked on a c-face sapphire substrate via a buffer layer are an undoped G
6043140 Method for growing a nitride compound semiconductor March 28, 2000
A new and improved method for growing a p-type nitride III-V compound semiconductor is provided which can produce a p-type nitride compound semiconductors having a high carrier concentration, without the need for annealing to activate impurities after growth. In a preferred embodiment,
5981980 Semiconductor laminating structure November 9, 1999
To provide a semiconductor laminating structure in which an epitaxial growth of a GaN system material is achieved on a substrate with an excellent matching property with the substrate. The semiconductor laminating structure includes the substrate having a perovskite structure and at
5929467 Field effect transistor with nitride compound July 27, 1999
A GaN-type field effect transistor exhibits a large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially laminated on a substrate with a buffer layer therebetween. A gate electrode is formed on the gate insulating film. A source
5863811 Method for growing single crystal III-V compound semiconductor layers on non single crystal III- January 26, 1999
A method for growing a single crystal III-V compound semiconductor layer, in which grown by vapor deposition on a first single crystal III-V compound semiconductor layer including at least Ga and N is a second single crystal III-V compound semiconductor layer different from the first
5821568 Cleaved semiconductor device with {11-20} plane October 13, 1998
A semiconductor device such as a semiconductor layer is formed of a compound semiconductor layer of III-V group such as GaN. In the case where the substrate has not any planes that are easy to cleave which coincides with an easy-to-cleave plane of a semiconductor layer grown on the s
5753966 Semiconductor device with cleaved surface May 19, 1998
A semiconductor light emitting device is prepared by the steps of forming a semiconductor layer 2 having a laminated structure containing at least a first cladding layer 6, a light emitting layer 7, and a second cladding layer 8 on a substrate 1 having {11-20} plane (plane a) as the main
5200021 Method and apparatus for vapor deposition April 6, 1993
A method for vapor deposition includes monitoring of growth of a semiconductor layer by way of in-situ monitoring. According to the invention, in-situ monitoring is performed by irradiating a light beam onto the surface of the growing layer in a direction nearly perpendicular to the
5140399 Heterojunction bipolar transistor and the manufacturing method thereof August 18, 1992
A heterojunction bipolar transistor formed as a collector top or emitter top type. This heterojunction bipolar transistor can operate at high speed and can be fabricated into a semiconductor integrated circuit with ease. The manufacturing method thereof is also disclosed.
4916499 Junction field effect transistor with vertical gate region April 10, 1990
A junction field effect transistor having a source region, a gate region and a drain region, which are laminated to form a laminated layer, and a channel region formed on one side surface across the laminated layer, and also having a cavity which separates high impurity concentration reg
4903104 Heterojunctional collector-top type bi-polar transistor February 20, 1990
A heterojunction type bi-polar transistor which has a heterojunction in the boundary between an intrinsic base region and an external base region to thereby eliminate the periphery effect and accordingly obtain a high current amplification factor.
4758870 Semiconductor device July 19, 1988
A III-V semiconductor device is disclosed, which includes an emitter region, an emitter barrier region having such a barrier height as to substantially restrict a thermionic emission current as compared with a tunneling current and such a barrier width as to permit the tunneling curr
4751195 Method of manufacturing a heterojunction bipolar transistor June 14, 1988
A method of manufacturing a heterojunction bipolar transistor in which a collector region, a base region and an emitter region are successively formed on a compound semiconductor substrate, forming the emitter region by epitaxial growth in a concave portion formed on an electrode leading


 
 
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