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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Kawaguchi; Kazuaki
Address:
Kawasaki, JP
No. of patents:
12
Patents:












Patent Number Title Of Patent Date Issued
8074144 Semiconductor storage device December 6, 2011
Plural data lines read normal data stored in a first area in the memory cell array when the data lines are connected to a selected bit line. Plural parity data lines read parity data from a second area in the memory cell array different from the first area, the parity data being used
7796461 Semiconductor device having a plurality of memory chips September 14, 2010
A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section configured to make
7697353 Semiconductor device April 13, 2010
A semiconductor device includes plural memory cell blocks, each having a memory array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written
7120078 Synchronous semiconductor memory October 10, 2006
In an FCRAM having a late write function, when a first command signal indicates "write active", whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates "writ
7102959 Synchronous semiconductor memory device of fast random cycle system and test method thereof September 5, 2006
An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal
7064988 Synchronous semiconductor memory device of fast random cycle system and test method thereof June 20, 2006
An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal
6973000 Synchronous semiconductor memory device of fast random cycle system and test method thereof December 6, 2005
An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal
6885606 Synchronous semiconductor memory device with a plurality of memory banks and method of controlli April 26, 2005
A synchronous semiconductor memory device includes a plurality of memory banks which read data from memory cells and write data into the memory cells, a command decoder circuit which receives a command, detects whether the command is a read command or a write command, and, when detecting
6879540 Synchronous semiconductor memory device having dynamic memory cells and operating method thereof April 12, 2005
A synchronous semiconductor memory device includes a memory cell array and a command decoder. In the memory cell array, dynamic memory cells are arranged in a matrix form. The command decoder decodes a plurality of commands in synchronism with an external clock signal. The plurality of
6826104 Synchronous semiconductor memory November 30, 2004
In an FCRAM having a late write function, when a first command signal indicates "write active", whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates "writ
6757214 Synchronous type semiconductor memory device June 29, 2004
A synchronous type semiconductor device which inputs/outputs data with respect to a host includes a memory circuit, command decoder and CAS latency setting circuit. The command decoder decodes a command control signal input from the host in synchronism with a clock input from the host
6731559 Synchronous semiconductor memory device May 4, 2004
A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing info










 
 
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