| Patent Number |
Title Of Patent |
Date Issued |
| 7484280 |
Method for manufacturing a surface acoustic wave element having an interdigital transducer (IDT) |
February 3, 2009 |
| A method for manufacturing a surface acoustic wave element having an interdigital transducer (IDT) electrode formed on a semiconductor substrate includes a) forming an insulation layer on a surface of an active side of the semiconductor substrate, b) forming a base layer on a whole s |
| 7015542 |
MONOS memory device |
March 21, 2006 |
| A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulatin |
| 6953967 |
Semiconductor device and method of manufacturing the same |
October 11, 2005 |
| A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating |
| 6930000 |
Method of manufacturing semiconductor device |
August 16, 2005 |
| The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has an element separating region formed on surface of a semiconductor layer to attain |
| 6888250 |
Semiconductor device, method for manufacturing the same, method for generating mask data, mask a |
May 3, 2005 |
| A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1 extending in a direction traversing the row |
| 6815291 |
Method of manufacturing semiconductor device |
November 9, 2004 |
| The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has a conductive layer to make a word gate of the non-volatile memory device, a stoppe |
| 6798015 |
Semiconductor device and method of manufacturing the same |
September 28, 2004 |
| A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a |
| 6762102 |
Methods for manufacturing semiconductor devices and semiconductor devices |
July 13, 2004 |
| Semiconductor devices and methods for manufacturing the same in which deterioration of electrical characteristics are suppressed are described. One method for manufacturing a semiconductor device includes the steps of: (a) forming a gate dielectric layer 20; (b) forming a polysilicon lay |
| 6706579 |
Method of manufacturing semiconductor device |
March 16, 2004 |
| The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method patterns a stopper layer and a first conductive layer in the memory area, while patterning the stopper layer and the first conductive |
| 6664155 |
Method of manufacturing semiconductor device with memory area and logic circuit area |
December 16, 2003 |
| The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has an element separating region formed on the surface of a semiconductor layer, a fir |
| 6605852 |
Semiconductor device and method for manufacturing the same including forming a plurality of dumm |
August 12, 2003 |
| A semiconductor device includes a silicon substrate 10 having a trench isolation region 24. A plurality of dummy convex regions 32 are formed in the trench isolation region 24. The trench isolation region 24 defines a row direction and a column direction. Also, the trench isolation regio |
| 6560765 |
Method for generating mask data, mask and computer readable recording media |
May 6, 2003 |
| A method is provided for generating mask data that is used for forming dummy convex regions in a specified pattern in a trench isolation region in a semiconductor device. Mask and computer readable recording medium are also provided. The method includes the steps of (a) setting a restric |
| 6404023 |
Semiconductor device having gate-gate, drain-drain, and drain-gate connecting layers and method |
June 11, 2002 |
| A semiconductor device comprising a peripheral circuit portion and a memory cell portion including a plurality of memory cells. Each memory cell has first and second gate-gate connecting layers, first and second drain-drain connecting layers, and first and second drain-gate connecting la |
