| Patent Number |
Title Of Patent |
Date Issued |
| 6751445 |
Receiver tuning system |
June 15, 2004 |
| In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer freq |
| 6665523 |
Receiver tuning system |
December 16, 2003 |
| In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer freq |
| 6064870 |
Interference detection circuit having amplitude frequency domain defined discrimination |
May 16, 2000 |
| An interference detection circuit includes a circuit, in particular a non-linear circuit, for defining a discrimination curve in terms of instantaneous magnitude and instantaneous frequency, and a circuit, in particular a differential amplifier, for detecting whether a combination, i |
| 5929678 |
Frequency synthesis circuit having a charge pump |
July 27, 1999 |
| A charge pump (CP) is provides for supplying at its output (23) a first current in response to an up-pulse and sinking a second current in response to a down pulse. This charge pump includes a first circuit 200, 22, CM1) for converting the first control signal into the first current, |
| 5839060 |
Logarithmic level detector and a radio receiver |
November 17, 1998 |
| A logarithmic level detector that provides a very accurate level detector output signal that is greatly insensitive to temperature and process spread. The logarithmic level detector includes a weighted summed reference circuit which is subtracted from a level output signal of the cas |
| 5809407 |
Receiver, an arrangement and a method for comparing two signals |
September 15, 1998 |
| A receiver, an arrangement and a method for comparing two signals, based on testing whether a first signal exhibits at least one property during a first time interval, and consecutively testing if a second signal exhibits at least one similar property during a second time interval, follo |
| 5715529 |
FM receiver including a phase-quadrature polyphase if filter |
February 3, 1998 |
| An FM receiver having an RF section, a first tunable mixer stage for the frequency conversion of a desired RF FM reception signal into a first intermediate frequency signal, an IF device and an FM demodulator. In order to enhance the integration of the apparatus, while maintaining a |
| 5572164 |
FM demodulator with threshold extension and receiver comprising such an FM demodulator |
November 5, 1996 |
| An FM demodulator having two input terminals (11, 12), to which FM input signals having 90.degree. phase relation are applied, the said FM demodulator including a phase comparator (1) and a tunable, phase shifting circuit (2), the phase shifting circuit (2) being tuned by the FM demo |
| 5548831 |
FM Receiver having multiple IF stages |
August 20, 1996 |
| An FM receiver includes an RF section, a first mixer stage for converting a desired RF reception signal into a first IF signal having a carrier frequency located on average at a first intermediate frequency, a first IF section for selecting the first IF signal, and a second mixer stage f |
| 5493250 |
Adjustable resistance device including first and second arrangements of a resistor and a positiv |
February 20, 1996 |
| An adjustable resistance device having a first parallel arrangement (1) of a first resistor and a first positive-feedback transconductor is provided with a control circuit (20) for controlling the controllable resistance section in the first parallel arrangement (1), which control circui |
| 5404589 |
FM receiver with dynamic intermediate frequency (IF) filter tuning |
April 4, 1995 |
| An FM receiver with a modulation signal-dependent intermediate frequency (IF) filter tuning, comprising a radio frequency (RF) section, a tunable mixer stage for a down-conversion of a desired RF FM reception signal to an intermediate frequency (IF) FM signal, an IF section comprising a |
| 5341107 |
FM quadrature demodulator with two phase comparison circuits |
August 23, 1994 |
| FM quadrature demodulator having in-phase and quadrature terminals for applying a pair of FM-modulated signals in a mutual phase quadrature thereto, having a modulation signal which is frequency-modulated on a carrier, one of the two terminals being coupled to a first input of a firs |
| 5221911 |
Receiver having PLL frequency synthesizer with RC loop filter |
June 22, 1993 |
| A receiver having an RF section, a mixer stage and a signal processing stage, the mixer stage receiving a mixing frequency from a frequency synthesis circuit which includes a phase-locked loop provided with a phase detection device having a current output, a loop filter including a . |
| 5113419 |
Digital shift register |
May 12, 1992 |
| In a digital shift register comprising a series of substantially identical bistable circuits, a reference voltage required for the bistable circuits is generated by coupling a common node to the outputs of the bistable circuits via resistors, in such a way that the reference voltage is t |
| 5093930 |
Directly mixing synchronous AM receiver |
March 3, 1992 |
| A directly mixing synchronous AM receiver includes a synchronous demodulator coupled to an antenna input for synchronously demodulating an RF-AM reception carrier and a phase-locked loop (PLL) incorporating a phase detection arrangement, a loop filter, a controllable oscillator which |
| 5093635 |
Controllable oscillator having transconductance circuits with amplitude stabilization |
March 3, 1992 |
| Controllable oscillator circuit comprising a regenerative loop which incorporates a cascade circuit of first and second sections each having a controllable gain and a phase shift which is 90.degree. at the oscillation frequency, and an amplitude detection arrangement which is coupled bet |
| 4973920 |
Controllable quadrature oscillator |
November 27, 1990 |
| A controllable quadrature oscillator, having a pair of oscillator outputs for supplying a pair of phase quadrature oscillator signals, is a cascade circuit of two quadrature sections incorporated in a regenerative loop each contributing a 90.degree. phase shift in the regenerative state |
| 4970469 |
Phase detector and frequency demodulator including such a phase detector |
November 13, 1990 |
| Phase detector having a first input for an angle-modulated input carrier to be detected, and a second input for a reference carrier having a phase shift which is dependent on the angle modulation with respect to the input carrier, the input and reference carriers being at least multiplie |
| 4903331 |
Quadrature detection receiver with separate amplitude and phase control |
February 20, 1990 |
| A pair of signal paths 3-1 and 3-2 are connected in parallel to an input 2, each composed of the respective mixing stages 4-1, 4-2, low-pass filters 5-1, 5-2 and mixing stages 6-1, 6-2. The mixing stages 4-1, 4-2 are connected to the oscillator 8 in a phase-quadrature relationship. The |
| 4814715 |
Mixer arrangement for suppression of oscillator interference in quadrature demodulators |
March 21, 1989 |
| Mixer arrangement (M) comprising first and second quadrature mixer stages (M.sub.1 and M.sub.2) to which quadrature mixing signals are applied from an oscillator circuit (F.sub.0), these two mixer stages (M.sub.1 and M.sub.2) being coupled to a superposition circuit (S.sub.0). To suppres |
| 4740759 |
Angle demodulator with second order interference prevention |
April 26, 1988 |
| Angle demodulator having a signal input (I) for applying an angle-modulated input carrier (A) thereto, which demodulator is coupled to a phase detection arrangement (2) to which also a quadrature detection carrier (D) frequency-coupled with the input carrier (A) is applied for demodulati |
| 4709163 |
Current-discrimination arrangement |
November 24, 1987 |
| A current-discrimination arrangement, in particular for use in stabilizing circuits, comprises two cross-coupled transistors. The current to be discriminated is applied in parallel to both transistors. For small currents both transistors conduct to the same extent, while at a current |
| 4642482 |
Level-shifting circuit |
February 10, 1987 |
| A level shifting circuit in which the collectors of a first transistor and a second transistor (T.sub.1, T.sub.2), which are coupled together as a differential pair, are each connected to a load resistor (R.sub.o) and to the base of a third transistor and a fourth transistor (T.sub.3, T. |
| 4639679 |
Frequency-doubling circuit |
January 27, 1987 |
| A frequency doubling circuit for doubling the fundamental frequency of a signal wave, comprising a pair of full-wave rectifier circuits which produce output signals which are subtracted to derive the second harmonic of the fundamental frequency. The direct current component and unwanted |
| 4636663 |
Double-balanced mixer circuit |
January 13, 1987 |
| A double-balanced RF mixer circuit comprising two differential amplifiers each of which comprises a pair of transistors the emitters of which are connected in common and the bases of which are cross-coupled to provide common first and second base terminals to which an oscillator signal i |
| 4633315 |
Receiver for RF-signals comprising a pair of parallel signal paths |
December 30, 1986 |
| A receiver for receiving a signal modulated on an RF-carrier, includes amplitude and phase control for reducing, to a very low value, deviations in the amplitude and phase correspondence of the signals in two signal paths therein in order to avoid an image interference signal due to |
| 4631499 |
Phase-locked loop for a directly mixing synchronous AM-receiver |
December 23, 1986 |
| A phase-locked loop is constituted by a controllable oscillator coupled through a phase detection arrangement and a low-pass filter to receive an input carrier applied to a signal input of the phase detection arrangement. In order to decrease the phase synchronization between a carri |
| 4625131 |
Attenuator circuit |
November 25, 1986 |
| A frequency-to-phase converter comprises an attenuator circuit (1), a delay circuit (2) and a comparator (3). The attenuator circuit (1) is provided with two transistors (T.sub.1, T.sub.2), which are arranged as a differential pair and whose collectors (9, 10) are coupled to the positive |
| 4587478 |
Temperature-compensated current source having current and voltage stabilizing circuits |
May 6, 1986 |
| A transconductance amplifier includes a differential amplifier, whose collector load is a current mirror having a current output. A current-source transistor arranged in the common emitter line supplies a current having a positive temperature-dependence. This current is obtained from |
| 4574257 |
Crystal resonator oscillator having circuitry for suppressing undesired crystal harmonics |
March 4, 1986 |
| Oscillator circuit comprising an amplifier arrangement being connected to a reference level an output and an input thereof being coupled via a single signal-carrying terminal to a resonant network which is connected to the same reference level as the amplifier arrangement, the resonant n |
| 4569085 |
Oscillator control circuit in an F.M. receiver |
February 4, 1986 |
| The invention relates to a circuit for an FM-receiver having a very low intermediate frequency and a tuning frequency-independent amplitude of the LF output signal. The oscillator frequency is controlled in such a way by a reactance circuit that frequency swing reduction occurs. In addit |
| 4554503 |
Current stabilizing circuit arrangement |
November 19, 1985 |
| A current stabilizing arrangement includes a first circuit having a series arrangement of a first resistor, a second resistor, and the collector-emitter path of a first transistor having its base connected to a point between the first and second resistors. A second circuit includes t |
| 4547902 |
Radio receiver comprising a frequency locked loop with audio frequency feedback, and a muting ci |
October 15, 1985 |
| Radio-receiver having a frequency-locked loop which comprises, a tunable voltage-controlled oscillator, a mixer stage, a filtering element, as well as a frequency-voltage converter which is connected to the tunable voltage-controlled oscillator. Several stable tunings are possible for |
| 4547744 |
Integrated amplifier arrangement |
October 15, 1985 |
| An integrated amplifier arrangement in which the d.c. voltage gain is suppressed, which includes two transistors arranged as a differential pair with an output between the collectors of these transistors. In order to improve the high-frequency properties of the amplifier arrangement, the |
| 4523328 |
FM-receiver including a frequency-locked loop |
June 11, 1985 |
| FM-receiver including a frequency-locked loop (2-14), which loop includes, successively connected, a voltage controlled oscillator (8), a mixer circuit (2) connected to an aerial input, an IF-portion comprising an IF-filter (9), an FM-detector (4), a loop filter (5) and a loop amplifier |
| 4509205 |
Radio receiver comprising a frequency locked loop with audio frequency feedback, and a muting ci |
April 2, 1985 |
| Radio-receiver having a frequency-locked loop which comprises, arranged one after the other, a tunable voltage-controlled oscillator, a mixer stage, a filtering element, as well as a frequency-voltage converter which is connected to the tunable voltage-controlled oscillator, several stab |
| 4426735 |
Radio receiver comprising a frequency locked loop with audio frequency feedback, and a muting ci |
January 17, 1984 |
| Radio-receiver having a frequency-locked loop which comprises, arranged one after the other, a tunable voltage-controlled oscillator, a mixer stage, a filtering element, as well as a frequency-voltage converter which is connected to the tunable voltage-controlled oscillator, several stab |
| 4242601 |
Circuit arrangement for frequency division |
December 30, 1980 |
| A wide-band frequency divider having a first and a second group of n transistors each, with their emitters in a first cyclic sequence alternately connected to the collectors of two transistors forming an input differential pair. The base electrode of any arbitrary transistor of said |
| 4123672 |
Circuit arrangement for frequency division of high-frequency pulses |
October 31, 1978 |
| A circuit arrangement for the frequency division of high frequency pulses in which a cyclic sequence of transistors are connected together via tapped resistances. In integrated circuit technology the tapped resistances may be the parasitic resistance of a semiconductor layer which se |
