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Inventor:
Kaneko; Mamoru
Address:
Osaka, JP
No. of patents:
1
Patents:












Patent Number Title Of Patent Date Issued
7651917 Semiconductor device and a method of manufacturing the same January 26, 2010
In the present invention, an npn junction is formed by circularly forming a p- type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With t










 
 
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