| Patent Number |
Title Of Patent |
Date Issued |
| 7075339 |
Semiconductor output circuit device |
July 11, 2006 |
| Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding output pull up trans |
| 6998879 |
Level determination circuit determining logic level of input signal |
February 14, 2006 |
| An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit |
| 6680866 |
Clock synchronous semiconductor memory device |
January 20, 2004 |
| The position information indicating the position of a memory relative to a controller is stored in a position information generating circuit, and the transfer timing of write data transmitted from an input circuit to a write circuit and the activation timing of a latch transfer instructi |
| 6621329 |
Semiconductor device |
September 16, 2003 |
| An external voltage is supplied to a power terminal of a semiconductor chip and is applied to a semiconductor circuit and a regulator circuit. An output control signal is supplied from semiconductor circuit to an output circuit. According to an RD signal output from semiconductor circuit |
| 6456563 |
Semiconductor memory device that operates in sychronization with a clock signal |
September 24, 2002 |
| An SDRAM is provided with a delay circuit for delaying for a certain time period a signal that attains an active level in response to an active command, and a latch circuit for latching an output signal of the delay circuit and generating a column decoder activating signal every time a |
| 6151273 |
Synchronous semiconductor memory device |
November 21, 2000 |
| A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In respo |
| 5659260 |
Sense amplifier having a circuit for compensating for potential voltage drops caused by parasiti |
August 19, 1997 |
| A negative power supply circuit is connected via an NMOS transistor to a node receiving ground potential in a sense amplifier. A one shot pulse generation circuit provides a one shot pulse signal to the gate of the NMOS transistor. The NMOS transistor is turned on when a one shot pulse |
| 5600281 |
Oscillator circuit generating a clock signal having a temperature dependent cycle and a semicond |
February 4, 1997 |
| In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference curren |
| 5557193 |
Stabilized voltage generating circuit and internal voltage down converter and a method of genera |
September 17, 1996 |
| A method and an apparatus of an internal voltage down converter having good transient response characteristics and small chip real estate, includes a differential amplifier for comparing a voltage on an internal power supply line with a reference voltage, a MOS transistor for generating |
| 5539353 |
Circuit for compensating for potential voltage drops caused by parasitic interconnection resista |
July 23, 1996 |
| A differential amplifier and an NMOS transistor are provided corresponding to each load circuit. A positive input and a negative input of the differential amplifier are coupled to a first ground interconnection and a second ground interconnection, respectively. When the selected load |
| 5530397 |
Reference voltage generating circuit of semiconductor memory device |
June 25, 1996 |
| A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power |
| 5499214 |
Oscillator circuit generating a clock signal having a temperature dependent cycle and a semicond |
March 12, 1996 |
| In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference curren |
| 5490119 |
Semiconductor device including signal generating circuit with level converting function and with |
February 6, 1996 |
| A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the |
| 5446418 |
Ring oscillator and constant voltage generation circuit |
August 29, 1995 |
| A ring oscillator according to the invention includes a plurality of inverters cascade-connected between an input node and an output node. Each inverter includes four transistors connected in series between a power supply node and a ground node. A first pair of transistors each have a |
| 5442277 |
Internal power supply circuit for generating internal power supply potential by lowering externa |
August 15, 1995 |
| An internal power supply circuit includes a main internal power supply potential generating circuit for generating an internal power supply potential based on a prescribed reference potential, and an auxiliary internal power supply potential generating circuit which is activated in r |
| 5436552 |
Clamping circuit for clamping a reference voltage at a predetermined level |
July 25, 1995 |
| A clamping circuit includes a constant current circuit including a constant current source and a current mirror circuit a trimmable resistance receiving a constant current from the constant current circuit, and a clamping MOS transistor receiving a voltage generated by the trimmable |
| 5412604 |
Semiconductor device using boosted signal |
May 2, 1995 |
| A level converting unit outputs a signal at a ground potential GND or at a boosted power supply voltage V.sub.PP level in response to a control signal. In response to a control signal BLIM, a first level selecting unit outputs a signal at the ground potential GND or at a power supply vol |
| 5391979 |
Constant current generating circuit for semiconductor devices |
February 21, 1995 |
| The constant current generating circuit includes a high resistance element for generating a very small current. This very small current is supplied to a first MOS transistor having a sufficiently large gate width to gate length ratio. The gate-source voltage of the first MOS transistor b |
| 5384745 |
Synchronous semiconductor memory device |
January 24, 1995 |
| Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local |
| 5381367 |
Semiconductor memory device and an operating method of the same |
January 10, 1995 |
| First and second input/output line groups are provided. A plurality of first bit line groups are connected to the first input/output line group through corresponding column selecting circuits, respectively. A plurality of second bit line groups are connected to the second input/output li |
| 5357416 |
Voltage generating circuit causing no threshold voltage loss by FET in output voltage |
October 18, 1994 |
| An improved substrate bias voltage generating circuit provided in a semiconductor device such as a DRAM is disclosed. In a conducting period of an NMOS transistor (8) provided in a last stage, a higher enough voltage than a source voltage (i.e. an output voltage V.sub.BB) can be appl |
