| Patent Number |
Title Of Patent |
Date Issued |
| 7573767 |
Semiconductor memory device |
August 11, 2009 |
| A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit |
| 7567474 |
Semiconductor storage device |
July 28, 2009 |
| A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and |
| 7554147 |
Memory device and manufacturing method thereof |
June 30, 2009 |
| A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM |
| 7515496 |
Self-refresh timer circuit and method of adjusting self-refresh timer period |
April 7, 2009 |
| A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control curren |
| 7511347 |
Semiconductor integrated circuit for high-speed, high-frequency signal transmission |
March 31, 2009 |
| A semiconductor integrated circuit comprising: a pair of MOS transistors which are formed in a same well on a semiconductor substrate and arranged adjacent to each other with a distance such that charge exchange between capacitances of respective drain diffusion layers is possible; and a |
| 7508707 |
Semiconductor storage apparatus |
March 24, 2009 |
| Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode o |
| 7486584 |
Semiconductor memory device and refresh control method thereof |
February 3, 2009 |
| A semiconductor memory device has a refresh control circuit for switchingly controlling a first refresh mode in which access to the memory cell array from outside is prohibited while retaining data and a second refresh mode in which access to the memory cell array from outside is per |
| 7471558 |
Semiconductor storage device |
December 30, 2008 |
| A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of t |
| 7449711 |
Phase-change-type semiconductor memory device |
November 11, 2008 |
| A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell |
| 7397695 |
Semiconductor memory apparatus and method for writing in the memory |
July 8, 2008 |
| A phase change memory of high compatibility with DRAM. If a cell MC0, connected to a word line WL0L, is of a low resistance, current flowing through it is higher than that flowing in a dummy cell MR0, and hence a bit line SA_B is at a potential lower than that of a bit line SA_T. This |
| 7333363 |
Semiconductor storage apparatus |
February 19, 2008 |
| Disclosed is a semiconductor storage apparatus in which two sorts of memories, that is, a volatile memory and a non-volatile memory, are mounted on one chip. Data of a DRAM memory array are saved in a corresponding area of a non-volatile memory before entry to a data retention mode o |
| 7317649 |
Semiconductor storage device |
January 8, 2008 |
| A semiconductor storage device comprising: unit blocks each including memory cells, first row of sense amplifiers on one side of bit lines; second row of sense amplifiers on an other side of the bit lines; first switch means which switches a connection state between the one side of t |
| 7307909 |
Self-refresh timer circuit and method of adjusting self-refresh timer period |
December 11, 2007 |
| A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control curren |
| 7307906 |
Semiconductor storage device |
December 11, 2007 |
| A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and |
| 7248528 |
Refresh control method of a semiconductor memory device and semiconductor memory device |
July 24, 2007 |
| A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, |
| 7193884 |
Semiconductor memory device |
March 20, 2007 |
| A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of |
| 6882557 |
Semiconductor memory device |
April 19, 2005 |
| The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.The switches are connected to one-side ends of the bit lines provided at the odd- |
| 4956811 |
Semiconductor memory |
September 11, 1990 |
| A semiconductor memory wherein an operating mode is selectively set by effecting bonding with respect to predetermined pads provided on a common semiconductor substrate in a predetermined combination or by cutting off predetermined fuse means provided on the common semiconductor substrat |
