| Patent Number |
Title Of Patent |
Date Issued |
| 6237108 |
Multiprocessor system having redundant shared memory configuration |
May 22, 2001 |
| A multiprocessor system having a redundant shared memory configuration includes a plurality of processors, each of which are connected to a shared system bus; and a plurality of shared system memory modules, e.g., dual shared system memory modules connected to the shared system bus. A |
| 6092173 |
Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data tra |
July 18, 2000 |
| A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The dire |
| 6038674 |
Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data tra |
March 14, 2000 |
| A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The dire |
| 5890217 |
Coherence apparatus for cache of multiprocessor |
March 30, 1999 |
| A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system |
| 5761728 |
Asynchronous access system controlling processing modules making requests to a shared system mem |
June 2, 1998 |
| An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a |
| 5737573 |
Asynchronous access system having an internal buffer control circuit which invalidates an intern |
April 7, 1998 |
| An asynchronous access system includes a system bus, at least one processing module provided with a main memory, a central processing unit and a first connection unit which connects to the system bus, and at least one shared memory module provided with a shared memory unit and a second |
| 5727151 |
Message control system specifying message storage buffer for data communication system with gene |
March 10, 1998 |
| A message control system is for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In this message control system, a memory u |
| 5708795 |
Asynchronous access system for multiprocessor system and processor module used in the asynchrono |
January 13, 1998 |
| In an asynchronous access system for a multiprocessor system having a plurality of processor modules connected to a system bus and at least one shared memory module connected to the system bus, each of the processor modules includes a processor and an internal buffer. The processor write |
| 5634037 |
Multiprocessor system having a shared memory with exclusive access for a requesting processor wh |
May 27, 1997 |
| An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the |
| 5592624 |
Data communication for controlling message transmission and reception among processing modules u |
January 7, 1997 |
| A message control system for a data communication system in the form of a loosely coupled multiprocessing system, in which a plurality of processing modules having a memory unit are coupled to each other via a system bus. In this message control system, a memory unit, within each process |
| 5410650 |
Message control system for data communication system |
April 25, 1995 |
| A message control system for a data communication system which takes the form of a loosely coupled multiprocessing system in which a plurality of processing modules respectively having a memory unit are coupled to each other via a system bus. In the message control system, each processin |
