| Patent Number |
Title Of Patent |
Date Issued |
| RE36490 |
Power and signal line bussing method for memory devices |
January 11, 2000 |
| A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is |
| 7334137 |
Memory interface systems that couple a memory to a memory controller and are responsive to a ter |
February 19, 2008 |
| Memory interface systems include one or more channel lines that couple a memory to a memory controller such that the channel line(s) are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller. Because the memory interface syst |
| 7246250 |
Memory device controls delay time of data input buffer in response to delay control information |
July 17, 2007 |
| An integrated circuit memory system includes one or more memory modules in which at least one of the memory modules is responsive to a control signal and has delay control information stored thereon. The memory system further includes a memory controller that is configured to generat |
| 6603686 |
Semiconductor memory device having different data rates in read operation and write operation |
August 5, 2003 |
| A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe |
| 6585525 |
Memory modules having conductors at edges thereof and configured to conduct signals to or from t |
July 1, 2003 |
| Memory modules, and related memory module sockets, can include a plurality of connector pins adjacent to a first edge of the memory module that are configured to conduct a plurality of first signals to or from the memory module via the first edge and a plurality of first conductors adjac |
| 6477110 |
Semiconductor memory device having different data rates in read operation and write operation |
November 5, 2002 |
| A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe |
| 6442057 |
Memory module for preventing skew between bus lines |
August 27, 2002 |
| A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit |
| 6275100 |
Reference voltage generators including first and second transistors of same conductivity type an |
August 14, 2001 |
| Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply |
| 6044017 |
Flash memory device |
March 28, 2000 |
| A flash memory includes an array of memory cells having sources, drains, floating gates, and control gates. The array includes a conductive plate formed over the memory cells to affect a capacitive coupling between the memory cells and the conductive plate. A first voltage source provide |
| 6040735 |
Reference voltage generators including first and second transistors of same conductivity type |
March 21, 2000 |
| Reference voltage generators can be made relatively insensitive to variations in threshold voltages due to device fabrication processes by providing first and second transistors of the same conductivity type that are connected to one another and between first and second power supply |
| 5963475 |
Advanced nonvolatile memories adaptable to dynamic random access memories and methods of operati |
October 5, 1999 |
| Disclosed is a nonvolatile memory, compatible with a dynamic random access memory, including a memory array divided into a plurality of blocks, each of the blocks being divided into a plurality of sub-blocks, reading and writing row decoders for selecting rows of the memory array, and re |
| 5677873 |
Methods of programming flash EEPROM integrated circuit memory devices to prevent inadvertent pro |
October 14, 1997 |
| Methods of programming flash EEPROM integrated circuit memory devices containing an array of NAND cells therein include the steps of applying a preselected logic signal to a select transistor of a NAND memory cell to inhibit the likelihood of inadvertent programming thereof when adjacent |
