| Patent Number |
Title Of Patent |
Date Issued |
| 7437007 |
Region-of-interest editing of a video stream in the compressed domain |
October 14, 2008 |
| The present invention, in one embodiment, is comprised of a method of performing region-of-interest editing of a video stream in the compressed domain. In accordance with this method, a video stream frame comprising an unwanted portion and a region-of-interest portion is received. The |
| 7336283 |
Efficient hardware A-buffer using three-dimensional allocation of fragment memory |
February 26, 2008 |
| A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined nu |
| 7184559 |
System and method for audio telepresence |
February 27, 2007 |
| A system and method for audio telepresence. The system includes a user station and a telepresence unit. The telepresence unit includes a directional microphone for capturing sounds at the remote location, and means for converting the captured sounds into a stream of data to be commun |
| 7093147 |
Dynamically selecting processor cores for overall power efficiency |
August 15, 2006 |
| A computer system for conserving operating power includes a number of computer hardware processor cores that differ amongst themselves in at least in their respective operating power requirements and processing capabilities. A monitor gathers performance metric information from each |
| 7064771 |
Method and apparatus for compositing colors of images using pixel fragments with Z and Z gradien |
June 20, 2006 |
| A graphics data processing apparatus includes a graphics memory having pixel storage for storing up to a predetermined number of fragment values for the pixel. Each stored fragment value is associated with a fragment of an image that is visible in that pixel. When a new fragment is d |
| 6781606 |
System and method for displaying images using foveal video |
August 24, 2004 |
| A high resolution image and at least two low resolution images are combined to produce a single image, partially high resolution, partially low resolution on a display. The high resolution image at least partially overlaps at least one of the low resolution images. This method of dis |
| 6633297 |
System and method for producing an antialiased image using a merge buffer |
October 14, 2003 |
| In a graphics pipeline, a rasterizer circuit generates fragments for an image having multiple surfaces that have been tessellated into primitive objects, such as triangles. First and second fragments are associated with the same pixel. A merge buffer merges the first fragment with the se |
| 6549215 |
System and method for displaying images using anamorphic video |
April 15, 2003 |
| An image is displayed using anamorphic video. A first portion of an image is displayed on a display at a first scale. At least one second portion of the image is displayed on the display. The at least one second portion is adjacent the first portion of the image. The second portion is di |
| 6346950 |
System and method for display images using anamorphic video |
February 12, 2002 |
| An image is displayed using anamorphic video. A first portion of an image is displayed on a display at a first scale. At least one second portion of the image is displayed on the display. The at least one second portion is adjacent the first portion of the image. The second portion is di |
| 6329977 |
Pre-filtered antialiased lines using distance functions |
December 11, 2001 |
| A computer graphics system renders an image on a display device using improved pre-filtering techniques that minimize aliasing artifacts in the image, particularly at the endpoints of lines. To anti-alias the image, a plurality of edges are placed near a line in the image. An edge functi |
| 6292713 |
Robotic telepresence system |
September 18, 2001 |
| A robotic telepresence system has a user station at a first geographic location and a robot at a second geographic location. The user station is responsive to a user and communicates information to and from the user. The robot is coupled to the user station and provides a three dimension |
| 6292193 |
Techniques for anisotropic texture mapping using multiple space-invariant filtering operations p |
September 18, 2001 |
| A computer graphics system maps textures to displayed anti-aliased images with surfaces defined at oblique angles to the viewer. A circular pixel filter is projected onto a texture map to define an elliptical footprint in that texture map. The elliptical footprint has a major axis. Sampl |
| 6204859 |
Method and apparatus for compositing colors of images with memory constraints for storing pixel |
March 20, 2001 |
| A method and an apparatus determine a color for pixels in a graphics system in which images are defined by pixels. Multiple fragments of an image may be visible in any given pixel. Each visible fragment has a fragment value that includes the color of that fragment. For such given pixel, |
| 6167503 |
Register and instruction controller for superscalar processor |
December 26, 2000 |
| In a superscalar computer system, a plurality of instructions are executed concurrently. The instructions being executed access data stored at addresses of the superscalar computer system. An instruction generator, such as a compiler, partitions the instructions into a plurality of sets. |
| 6128000 |
Full-scene antialiasing using improved supersampling techniques |
October 3, 2000 |
| A method and an apparatus reduces aliasing artifacts in images defined by pixels. A pixel is partitioned into subpixel locations from which sample points are selected. A fragment of the image is determined to be visible at at least one of the sample points. A fragment value associated wi |
| 6112318 |
Performance counters controlled by programmable logic |
August 29, 2000 |
| An apparatus and method for counting event signals generated by a computer system is described. The event signals are indicative of the performance of the computer system. Programmable logic enhances the functionality of performance counters by enabling the system user to specify, during |
| 6109777 |
Division with limited carry-propagation in quotient accumulation |
August 29, 2000 |
| A computing system performs non-restoring division. Quotient selection logic selects quotient digits that are used to produce a final quotient. The quotient digits are selected according to a predetermined relationship among certain bits of the divisor and the partial remainder. Only non |
| 6065033 |
Wallace-tree multipliers using half and full adders |
May 16, 2000 |
| An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of different columns differing in orders of magnitude. The apparatus includes one or more full |
| 5958040 |
Adaptive stream buffers |
September 28, 1999 |
| The invention is a system providing adaptive stream buffers using instruction-specific prefetching avoidance (ISPA). According to the invention, each time the CPU executes an instruction resulting in prefetched cache lines not being used, the instruction address is stored in a table. |
| 5870109 |
Graphic system with read/write overlap detector |
February 9, 1999 |
| A graphics system for storing and editing graphic images represented by digital data, includes a frame memory for storing pixel data representing graphic images including first and second graphic objects. The pixel data is stored at addresses, each being associated with one or more graph |
| 5787465 |
Destination indexed miss status holding registers |
July 28, 1998 |
| A hierarchical memory arrangement for use with a processor includes a cache, addressable by source addresses, and a set of processor registers, addressable by destination addresses. For each processor register there is a miss status holding registers. If the cache does not store data |
| 5629840 |
High powered die with bus bars |
May 13, 1997 |
| Power bus bars are provided for a semiconductor die. Power bus bars are thick electrical conductors that extend the length of the die in an electrically isolated array of stripes. The electrical stripes are divided into two or more interdigitated groups, each group connected to a power |
| 5582242 |
Thermosiphon for cooling a high power die |
December 10, 1996 |
| A thermosiphon provides cooling for a high powered die. The thermosiphon includes a fuse for accommodating temperature fault conditions. The thermosiphon utilizes a water and alcohol mixture for improved boiling characteristics. Contaminants at the joint betweeen the thermosiphon and |
| 5386547 |
System and method for exclusive two-level caching |
January 31, 1995 |
| A simple mixed first level cache memory system (50) includes a level 1 cache (52) connected to a processor (54)by read data and write data lines (56) and (58). The level 1 cache (52) is connected to level 2 cache (60) by swap tag lines (62) and (64), swap data lines (66) and (68), mu |
| 5317718 |
Data processing system and method with prefetch buffers |
May 31, 1994 |
| A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss |
| 5261113 |
Apparatus and method for single operand register array for vector and scalar data processing ope |
November 9, 1993 |
| In a data processing system in which a processing unit can execute both scalar and vector instructions, the use of a single operand register file to store both the scalar operation operands and the vector operation operands is described. An instruction is included in the instruction |
| 5261066 |
Data processing system and method with small fully-associative cache and prefetch buffers |
November 9, 1993 |
| A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss |
| 5150469 |
System and method for processor pipeline control by selective signal deassertion |
September 22, 1992 |
| A processor pipeline control system and method provides a complete set of very simple and very fast pipeline control signals encompassing stalls and interrupts. Each pipeline stage has associated with it a signal called "LoadX", where X is the pipeline stage name, e.g., LoadID. Instead o |
| 4999803 |
Floating point arithmetic system and method |
March 12, 1991 |
| System and method for reducing the processing time or latency of floating point arithmetic operations by eliminating the need to complement a negative result produced by a subtraction operation. Each of two numbers is subtracted from the other in simultaneous parallel subtraction ope |
