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Inventor:
Jones; Ian W.
Address:
Palo Alto, CA
No. of patents:
15
Patents:












Patent Number Title Of Patent Date Issued
7464229 Serial-write, random-access read, memory December 9, 2008
A serial-write, random-access read, memory addresses applications where the data in the memory may change more frequently than would make a PROM suitable, but that changes much less frequently than would require a RAM. This enables the circuit designer to optimize the memory for fast rea
7436861 Asynchronous control circuit with symmetric forward and reverse latencies October 14, 2008
One embodiment of the present invention provides a control queue for an asynchronous circuit that includes a number of control modules coupled together linearly to form the control queue. These control modules include a prior module, a present module, and a next module. The present m
7383459 Apparatus and method for phase-buffering on a bit-by-bit basis using control queues June 3, 2008
One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the control queue is configured to accept both a first control signal and a second control s
7296176 Method and apparatus for limiting the number of asynchronous events that occur during a clock cy November 13, 2007
One embodiment of the present invention provides a system that limits a maximum repetition rate of an asynchronous circuit. The system operates by receiving a clock signal at a rate-controlling circuit for the asynchronous circuit from a source external to the asynchronous circuit. T
6882645 Apparatus and method for sequencing memory operations in an asynchronous switch fabric April 19, 2005
One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system includes a memory device, which does not preserve first-in, first-out semantics such as a random access memory or a stack. The syste
6847247 Jittery polyphase clock January 25, 2005
A plurality of clock signal phases are distributed to a circuit and at least one jitter source is coupled between at least two selected clock phases of the plurality of clock signal phases to introduce a jitter between at least the selected two clock signal phases. In a specific embo
6772243 Apparatus and method for generating a partial fullness indicator signal in a FIFO August 3, 2004
Techniques for indicating partial fullness levels of a FIFO comprising a plurality of stages using a partial fullness detector, such as a m-out-of-n detector. According to an embodiment, the m-out-of-n detector is coupled to "n" stages of the FIFO and configured to output a partial f
6741616 Switch fabric for asynchronously transferring data within a circuit May 25, 2004
One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of
6675246 Sharing arbiter January 6, 2004
The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before receiving a Done signal. A Sharing ar
6557161 Method for prototyping asynchronous circuits using synchronous devices April 29, 2003
One embodiment of the present invention provides a system that facilitates prototyping asynchronous circuits. The system first receives a design of an asynchronous circuit, which includes asynchronous cells. The system maps the asynchronous cells of the asynchronous circuit onto clocked
6085316 Layered counterflow pipeline processor with anticipatory control July 4, 2000
A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to th
6072805 Observing arbiter June 6, 2000
An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a first input connection and a second input connection for carrying the signals indicative of events. A first input queue for sto
5875339 Asynchronous arbiter using multiple arbiter elements to enhance speed February 23, 1999
An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination of request signals and their complements and grant signals and their complements fed back from the output of the arbiter circu
5838933 Control circuit and method for a first-in first-out data pipeline November 17, 1998
Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the
5713025 Asynchronous arbiter using multiple arbiter elements to enhance speed January 27, 1998
An arbiter circuit is described that is capable of granting a first user access to a shared resource while concurrently arbitrating subsequent requests from the first user to other users seeking access to the shared resource. The arbiter of the present invention includes a first arbiter










 
 
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