| Patent Number |
Title Of Patent |
Date Issued |
| 7473599 |
Memory capable of storing information and the method of forming and operating the same |
January 6, 2009 |
| A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remov |
| 7457154 |
High density memory array system |
November 25, 2008 |
| A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or |
| 7375394 |
Fringing field induced localized charge trapping memory |
May 20, 2008 |
| The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall |
| 7235848 |
Nonvolatile memory with spacer trapping structure |
June 26, 2007 |
| The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sid |
| 7179708 |
Process for fabricating non-volatile memory by tilt-angle ion implantation |
February 20, 2007 |
| A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more |
| 7072210 |
Memory array |
July 4, 2006 |
| A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to |
| 7030448 |
Mask ROM and the method of forming the same and the scheme of reading the device |
April 18, 2006 |
| The structure of the nonvolatile memory includes a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric laye |
| 6903968 |
Nonvolatile memory capable of storing multibits binary information and the method of forming the |
June 7, 2005 |
| A nonvolatile memory capable of storing multi-bits binary information is provided. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to a |
| 6885072 |
Nonvolatile memory with undercut trapping structure |
April 26, 2005 |
| The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a |
| 6740927 |
Nonvolatile memory capable of storing multibits binary information and the method of forming the |
May 25, 2004 |
| A nonvolatile memory capable of storing multi-bits binary information is provide. The memory includes an oxide formed on a substrate. A control gate is formed on the oxide. An L-shape structure is attached on sidewall of the control gate. Spacers are formed on the L-shape structure to ac |
| 6278189 |
High density integrated circuits using tapered and self-aligned contacts |
August 21, 2001 |
| A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with red |
| 6239011 |
Method of self-aligned contact hole etching by fluorine-containing discharges |
May 29, 2001 |
| The practice of forming self-aligned contacts (SACs) in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitrid |
| 6211557 |
Contact structure using taper contact etching and polycide step |
April 3, 2001 |
| A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structur |
| 6168987 |
Method for fabricating crown-shaped capacitor structures |
January 2, 2001 |
| The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate |
| 6103588 |
Method of forming a contact hole in a semiconductor device |
August 15, 2000 |
| The present invention includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the |
| 6037276 |
Method for improving patterning of a conductive layer in an integrated circuit |
March 14, 2000 |
| A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhan |
| 6037211 |
Method of fabricating contact holes in high density integrated circuits using polysilicon landin |
March 14, 2000 |
| A method of fabricating contact holes in high density integrated circuits uses landing plugs to reduce the aspect ratio of the the node contact holes in order to improve the processing window of deep contact holes. Along with nitride spacers on the sidewalls of a transistor gate stru |
| 5994228 |
Method of fabricating contact holes in high density integrated circuits using taper contact and |
November 30, 1999 |
| A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with red |
| 5962195 |
Method for controlling linewidth by etching bottom anti-reflective coating |
October 5, 1999 |
| A method for forming a patterned target layer within an integrated circuit. The method employs a plasma pre-treatment of a patterned photoresist layer employed in patterning a blanket focusing which in turn is employed in patterning the patterned target layer from a blanket target layer. |
| 5952156 |
Enhanced reflectivity coating (ERC) for narrow aperture width contact and interconnection lithog |
September 14, 1999 |
| A method for forming for use within an integrated circuit a narrow aperture width patterned positive photoresist layer from a blanket positive photoresist layer. There is first formed over a semiconductor substrate a reflective layer. There is then formed upon the reflective layer a blan |
| 5915198 |
Contact process using taper contact etching and polycide step |
June 22, 1999 |
| A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structur |
| 5905293 |
LDD spacers in MOS devices with double spacers |
May 18, 1999 |
| In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor |
| 5904521 |
Method of forming a dynamic random access memory |
May 18, 1999 |
| A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and |
| 5834359 |
Method of forming an isolation region in a semiconductor substrate |
November 10, 1998 |
| A method for forming an isolation region in a semiconductor substrate is disclosed. The present invention includes forming an insulating layer on the semiconductor substrate, and then forming a dielectric layer on the insulating layer. After patterning to etch portions of the dielectric |
| 5817579 |
Two step plasma etch method for forming self aligned contact |
October 6, 1998 |
| A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon |
| 5804852 |
Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode |
September 8, 1998 |
| A multiple crown shaped polysilicon structure, used for a lower electrode of a DRAM stacked capacitor structure, has been developed. The multiple crown shaped, lower electrode, is formed overlying, and contacting a polysilicon fill layer, that is located between insulator encapsulated |
| 5804489 |
Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etch |
September 8, 1998 |
| The present invention is a method of manufacturing crown shape capacitors in the semiconducter memories. Using a single step etching to farbricate the capacitor in a DRAM cell. The method can form side wall polymers and etching byproductions on the surface of the first polysilicon, using |
| 5792689 |
Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random |
August 11, 1998 |
| A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node co |
| 5792687 |
Method for fabricating high density integrated circuits using oxide and polysilicon spacers |
August 11, 1998 |
| The preset invention provides a method of manufacturing miniature interconnects and capacitors for semiconductor memory devices. The method uses a configuration of two sets of spacers to form self aligned source/bit line contacts and capacitor storage electrodes. First spacers are fo |
| 5789289 |
Method for fabricating vertical fin capacitor structures |
August 4, 1998 |
| A unique DRAM structure has increased capacitance by using a parallel fin capacitor structure. A preferred embodiment of the invention includes a silicon substrate having a first conductivity type. Field oxide (FOX) regions are defined in the substrate to separate DRAM cells. Drain and |
| 5780338 |
Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated cir |
July 14, 1998 |
| A method for manufacturing crown-shaped stacked capacitors on dynamic random access memory using a single photoresist mask to make the node contacts and capacitor bottom electrodes was achieved. After forming the FET gate electrodes from a first polysilicon layer and the bit lines from |
| 5763312 |
Method of fabricating LDD spacers in MOS devices with double spacers and device manufactured the |
June 9, 1998 |
| In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor |
| 5721154 |
Method for fabricating a four fin capacitor structure |
February 24, 1998 |
| A unique DRAM structure has increased capacitance by using a four parallel fin capacitor structure. A preferred method for fabricating the DRAM is disclosed. DRAM cell is formed on a silicon substrate having a first conductivity type. Field oxide (FOX) regions are defined in the substrat |
| 5710073 |
Method for forming interconnections and conductors for high density integrated circuits |
January 20, 1998 |
| The present invention provides a method of manufacturing miniature interconnect for semiconductor devices. The method uses a configuration of spacers and etch barriers (silicon nitride cap layers) to form self aligned source and drain contacts. Antireflective silicon nitride cap laye |
| 5706164 |
Method of fabricating high density integrated circuits, containing stacked capacitor DRAM device |
January 6, 1998 |
| A process for fabricating stacked capacitor structure, DRAM devices, has been developed, in which the surface area of the stacked capacitor structure has been increased as a result of the topography created via the use of underlying insulator filled, shallow trenches, insulator protected |
| 5677227 |
Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, us |
October 14, 1997 |
| A process for creating a stacked capacitor, dynamic random access memory device, featuring increased capacitor surface area, resulting from a polysilicon, triple crown shaped, lower electrode structure, and also featuring self-alignment of the stacked capacitor contact structure, to a |
| 5658830 |
Method for fabricating interconnecting lines and contacts using conformal deposition |
August 19, 1997 |
| The present invention is a method for fabricating interconnecting lines and contacts using conformal deposition. This invention applies patterning trenches simultaneously for interconnecting lines and contact holes and forming spacers technologies to make fully filled interconnecting lin |
