| Patent Number |
Title Of Patent |
Date Issued |
| RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pi |
September 22, 2009 |
| A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered trans |
| 6298410 |
Apparatus and method for initiating hardware priority management by software controlled register |
October 2, 2001 |
| An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt |
| 6292906 |
Method and apparatus for detecting and compensating for certain snoop errors in a system with mu |
September 18, 2001 |
| A method and apparatus for handling cache snoop errors. According to one method disclosed, a snoop cycle having a snoop address is generated by a first bus agent. A second bus agent detects a snoop error in response to that bus cycle. As a result of the detected snoop error, the snoop er |
| 6260091 |
Method and apparatus for performing out-of-order bus operations in which an agent only arbitrate |
July 10, 2001 |
| A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase. |
| 6108781 |
Bootstrap processor selection architecture in SMP system |
August 22, 2000 |
| A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity |
| 6021458 |
Method and apparatus for handling multiple level-triggered and edge-triggered interrupts |
February 1, 2000 |
| Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a |
| 6012118 |
Method and apparatus for performing bus operations in a computer system using deferred replies r |
January 4, 2000 |
| A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase. |
| 5964856 |
Mechanism for data strobe pre-driving during master changeover on a parallel bus |
October 12, 1999 |
| In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:providing a first strobe signal and a second strobe signal for synchronizing said |
| 5961621 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pi |
October 5, 1999 |
| A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered trans |
| 5951663 |
Method and apparatus for tracking bus transactions |
September 14, 1999 |
| A method and device for tracking a bus transaction between first and second agents coupled to a bus includes issuing a request for the transaction by the first agent, storing information regarding the transaction in a buffer, and deleting the information regarding the transaction from th |
| 5904733 |
Bootstrap processor selection architecture in SMP systems |
May 18, 1999 |
| A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity |
| 5889978 |
Emulation of interrupt control mechanism in a multiprocessor system |
March 30, 1999 |
| A multiprocessor computer system that includes an emulation feature for lowest priority processor software compatibility while providing fault tolerance includes first and second processors coupled to a system bus that handles transmission of interruption messages within the system. An |
| 5848279 |
Mechanism for delivering interrupt messages |
December 8, 1998 |
| An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with |
