| Patent Number |
Title Of Patent |
Date Issued |
| RE38514 |
System for and method of efficiently controlling memory accesses in a multiprocessor computer sy |
May 11, 2004 |
| A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that th |
| 7474586 |
Random access memory (RAM) method of operation and device for search engine systems |
January 6, 2009 |
| A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) ma |
| 7401180 |
Content addressable memory (CAM) device having selectable access and method therefor |
July 15, 2008 |
| According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular s |
| 7379352 |
Random access memory (RAM) method of operation and device for search engine systems |
May 27, 2008 |
| A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) ma |
| 7321592 |
Method of and apparatus for implementing and sending an asynchronous control mechanism packet us |
January 22, 2008 |
| An asynchronous control mechanism packet is used to send control messages and information to one or more bridge devices within a network of buses of devices. The asynchronous control mechanism packet is addressed to a device on one of the buses and is intercepted by one or more appropria |
| 7301961 |
Method and apparatus for configuring signal lines according to idle codes |
November 27, 2007 |
| A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, |
| 7283565 |
Method and apparatus for framing a data packet |
October 16, 2007 |
| According to a data packet framing method of one embodiment, a data packet (100) may include a combination control character (102) that may convey framing information FLAG (102-0) and a code information CODE (102-1). Framing information FLAG (102-0) can indicate a start of a packet, and |
| 7185141 |
Apparatus and method for associating information values with portions of a content addressable m |
February 27, 2007 |
| According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programmable information registers (PIRs) (104-0 and 104-1), each of |
| 7117301 |
Packet based communication for content addressable memory (CAM) devices and systems |
October 3, 2006 |
| A search engine system (100) and CAM device (300) are disclosed. A search engine system (100) may generate response packets (112) in response to requests packets (110) and include at least one content addressable memory (CAM) device (102-0) having an input interface (116-0) for recei |
| 7117300 |
Method and apparatus for restricted search operation in content addressable memory (CAM) devices |
October 3, 2006 |
| According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a "restricted" search operation. A restricted search operation (an "explore" or "search beyond" operation) may compare only a portion of the CAM entries to a search key device. Pre |
| 7085480 |
AV/C commands for accessing a hard disk device |
August 1, 2006 |
| A method and system thereof for organizing and accessing stored data in a mass storage unit such as a hard disk device. An object is associated with the stored data, and a unique object identifier is derived for and assigned to the object by the hard disk device. The object is addressed |
| 7073018 |
Device identification method for systems having multiple device branches |
July 4, 2006 |
| A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (106-0 to 106-5) in a system (100) having multiple branches (112-0 and 112-1). After chip IDs have been assigned to chips of a first branch (112-0) a command processing |
| 6993022 |
Method of and apparatus for directly mapping communications through a router between nodes on di |
January 31, 2006 |
| Within the routing method and apparatus of the present invention, a router is coupled to multiple buses, each of the buses having one or more nodes. A node on a first bus structure sending a communication to a node on a second bus structure includes an address value within the communicat |
| 6954823 |
Search engine device and method for generating output search responses from multiple input searc |
October 11, 2005 |
| According to one embodiment, a search engine device (100) may include an input (102), search portion (106), and a vote portion (108). A vote portion (108) may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion (1 |
| 6928646 |
System and method for efficiently performing scheduling operations in an electronic device |
August 9, 2005 |
| A system and method for efficiently performing scheduling operations in an electronic device comprises an allocation manager that initially evaluates a task scheduling request based upon certain request parameters. The request parameters may include a resource requirement and an executio |
| 6910090 |
Maintaining communications in a bus bridge interconnect |
June 21, 2005 |
| A method of maintaining communications in a bus bridge interconnect including a plurality of buses linked by at least one bus bridge. The method includes receiving a change indication signal from a talker node, performing an address resolution protocol in response to the change indic |
| 6906936 |
Data preclassifier method and apparatus for content addressable memory (CAM) device |
June 14, 2005 |
| A content addressable memory (CAM) device (100) may include a CAM array (102), a CAM array access circuit (104), and a preclassifier circuit (106). A preclassifier circuit (106) may selectively modify portions of an input data value before such an input data value is applied to a CAM arr |
| 6903951 |
Content addressable memory (CAM) device decoder circuit |
June 7, 2005 |
| A decoder circuit (100) is disclosed that may include "string" decoders (102-0 and 102-1), a compare circuit (104) and an enable circuit (106). String decoders (102-0 and 102-1) may provide "one-hot" or "string" decoding. One-hot decoding may activate one pre-decode signal. String de |
| 6898201 |
Apparatus and method for inter-node communication |
May 24, 2005 |
| A first set of signals is transformed into a second set of signals having a more stable set of current requirements. The more stable current requirements of the second set of signals are achieved by encoding the second set of signals with either an equal number, nearly an equal number, |
| 6892273 |
Method and apparatus for storing mask values in a content addressable memory (CAM) device |
May 10, 2005 |
| According to one embodiment, a method for storing content addressable memory (CAM) mask values may include storing mask values according to mask size in a mask register set (200). A mask register set (200) may include a number of locations arranged into regions (202, 204, 206 and 208). E |
| 6879523 |
Random access memory (RAM) method of operation and device for search engine systems |
April 12, 2005 |
| A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) ma |
| 6876558 |
Method and apparatus for identifying content addressable memory device results for multiple requ |
April 5, 2005 |
| A system (100) may include a content addressable memory (CAM) device (102) and at least two requesting devices (104-0 and 104-n). Requesting devices (104-0 and 104-n) and a CAM device (102) may be connected by at least two communication links (106-0 and 106-n). A CAM device (102) may gen |
| 6847650 |
System and method for utilizing a memory device to support isochronous processes |
January 25, 2005 |
| A system and method for utilizing a memory device to support isochronous processes comprises a memory device that may be partitioned to provide an isochronous memory for storing high-priority isochronous information, and a processor device for accessing and utilizing the isochronous info |
| 6845024 |
Result compare circuit and method for content addressable memory (CAM) device |
January 18, 2005 |
| A content addressable memory (CAM) device (100) may include a number of blocks (102-[n-1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n-1, n, n+1] that receive CAM search results from multiple blocks (102-[n-1, n, n-1]), and compare at least a portion |
| 6810452 |
Method and system for quarantine during bus topology configuration |
October 26, 2004 |
| A method and system for quarantine during bus topology configuration are described. In one embodiment, the invention is a method. The method includes quarantining a set of devices coupled to a bus. The method further includes establishing a topology of the bus. The method may also in |
| 6763426 |
Cascadable content addressable memory (CAM) device and architecture |
July 13, 2004 |
| According to one embodiment, a CAM system (100) may include a plurality of CAM devices (102-0 to 102-n) arranged in cascade configuration. A CAM system (100) may include an input connection (104) that receives a request to perform a particular operation and an output connection (106) on |
| 6684315 |
Method and system for supporting multiprocessor TLB-purge instructions using directed write tran |
January 27, 2004 |
| A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked |
| 6647446 |
Method and system for using a new bus identifier resulting from a bus topology change |
November 11, 2003 |
| A method and system for using a new bus identifier in an interconnect, and the interconnect including a plurality of nodes and at least one bus bridge. A configuration change is determined on the first bus connected to the plurality of nodes. Each node has a corresponding bus identifier. |
| 6584550 |
System and method for updating a head entry from read-only to read-write and allowing a list to |
June 24, 2003 |
| In a multi-processor system having cache-coherent sharing list, initiating a request to obtain a read-write copy updates a head of a cache sharing list from read-only status to read-write status. If another cache joins the list before the updating transaction has been completed, the pres |
| 6584539 |
Method and system for message broadcast flow control on a bus bridge interconnect |
June 24, 2003 |
| A method and system for distributing messages on a bus bridge interconnect are described. In one embodiment, the interconnect comprises a number of nodes, a bus bridge, and a number of buses. The method and system insure that the messages have been observed by each node. In one embodimen |
| 6567896 |
System and method for deleting read-only head entries in multi-processor computer systems suppor |
May 20, 2003 |
| A method and system for deleting a head entry of a read-only list in a multi-processor computer system supporting mixed cache-coherence protocols involving both read-only and read-write processors. The head of the list first informs the next-list entry that the next-list entry is about t |
| 6557067 |
System and method to effectively compensate for delays in an electronic interconnect |
April 29, 2003 |
| A system and method to effectively compensate for delays in an electronic interconnect comprises a controller that initially schedules a first transmission from a first talker device to several listener devices. The controller then schedules a second talker device to pre-roll a second |
| 6539450 |
Method and system for adjusting isochronous bandwidths on a bus |
March 25, 2003 |
| A method and system for adjusting the bandwidth allocated for isochronous data traffic on an interconnected data bus is disclosed. The present system uses an isochronous resource manager (IRM) to sense a bandwidth change request from a talker. The IRM instigates a bandwidth adjustment |
| 6502158 |
Method and system for address spaces |
December 31, 2002 |
| A system for allowing a node to be accessed through multiple address spaces. The system includes a virtual address memory providing a software settable bus identification address and a stable node identification address for each node in a net, a physical address memory providing a ph |
| 6496907 |
System and method for updating from a read-only to a read-write entry and concurrently invalidat |
December 17, 2002 |
| Cache-coherence computer systems represent cache-lines associated with their processors by linked and shared lists, which can be read-only or read-write. In read-only lists all cache-line copies are the same and may be read by multiple processors at the same time, while read-write lists |
| 6445711 |
Method of and apparatus for implementing and sending an asynchronous control mechanism packet us |
September 3, 2002 |
| An asynchronous control mechanism packet is used to send control messages and information to one or more bridge devices within a network of buses of devices. The asynchronous control mechanism packet is addressed to a device on one of the buses and is intercepted by one or more appropria |
| 6442644 |
Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
August 27, 2002 |
| A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair o |
| 6421745 |
Asynchronous connections with scattering page tables for transmitting data from a producer devic |
July 16, 2002 |
| Both small frames and large frames of data are transmitted from a producer device to a consumer device over an IEEE 1394 serial data bus. The small frames of data are preferably transmitted to a small frame buffer associated with a plug at the consumer device. Each transfer of a small |
| 6414971 |
System and method for delivering data packets in an electronic interconnect |
July 2, 2002 |
| A system and method for delivering data packets in an electronic interconnect comprises a talker device that transmits one or more data packets over a transmission path to a listener device through one or more bus bridges that each couple adjacent busses in the electronic interconnec |
| 6374316 |
Method and system for circumscribing a topology to form ring structures |
April 16, 2002 |
| A method and system for ordering an interconnect topology to form a ring structure, the topology comprising a number of nodes, are described. In one embodiment, a self identifier for each of the nodes is determined. Further, the self identifier is mapped to a ring identifier for each nod |
| 6345352 |
Method and system for supporting multiprocessor TLB-purge instructions using directed write tran |
February 5, 2002 |
| A method and system for purging translation lookaside buffers (TLB) of a computer system are described. Directed write transactions can be used to avoid deadlock and avoid the need for additional bridge buffers. Broadcast emulation can be achieved by linking the nodes in a doubly-linked |
| 6321304 |
System and method for deleting read-only head entries in multi-processor computer systems suppor |
November 20, 2001 |
| In a mixed-protocol multiple-processor cache coherence computer system one processor may support read-only and read-write lists while another processor may support only read-write lists. Data copied to a cache is called a cache line while a copy of the same data remaining in memory is |
| 6286067 |
Method and system for the simplification of leaf-limited bridges |
September 4, 2001 |
| A method of address management in a net having a plurality of buses linked by a plurality of bus bridges where the net has only one branch bus with multiple bus bridges. A local identification address is assigned to each node on a branch bus and a bus number is assigned to each bus other |
| 6249827 |
Method for transferring data associated with a read/write command between a processor and a read |
June 19, 2001 |
| A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks |
| 6226723 |
Bifurcated data and command/address communication bus architecture for random access memories em |
May 1, 2001 |
| A computer memory device featuring a high-bandwidth memory interface to transfer information between a controller and the memory cells of a memory modules. Bifurcated communication buses is provided to take advantage of the interface. One of the bifurcated communication busses is dedicat |
| 6208645 |
Time multiplexing of cyclic redundancy functions in point-to-point ringlet-based computer system |
March 27, 2001 |
| A method and system for providing cyclic redundancy check (CRC) functions within a ringlet-type interconnect of a computer system are described. By time multiplexing CRC checking and generating functions, the number of CRC units can be reduced. |
| 6133938 |
Descriptor mechanism for assuring indivisible execution of AV/C operations |
October 17, 2000 |
| A system for implementing indivisible command execution in an AV/C home audio video network of connected network devices. A network bus operable for conveying commands among a plurality of coupled devices is coupled to each of the devices. A controller device is coupled to the network bu |
| 6108739 |
Method and system for avoiding starvation and deadlocks in a split-response interconnect of a co |
August 22, 2000 |
| A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing |
| 6035376 |
System and method for changing the states of directory-based caches and memories from read/write |
March 7, 2000 |
| A system for converting between the states of fresh and owned in a multi-processor computer system comprises a memory line with a structure including a first field for storing a memory state, a second field for storing an address, and a third field for storing data. Each of the cache |
| 6006289 |
System for transferring data specified in a transaction request as a plurality of move transacti |
December 21, 1999 |
| A system and method for coordinating the transmission and receipt of large data blocks as a series of smaller burst transfers through an intermediate interconnect coupling a pair of devices. A device receiving a transaction request ("initiator") specifies the data block size of the reque |
