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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Jain; Kailash C.
Address:
Sterling Heights, MI
No. of patents:
7
Patents:












Patent Number Title Of Patent Date Issued
4948757 Method for fabricating three-dimensional microstructures and a high-sensitivity integrated vibra August 14, 1990
A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is patterned to produce a micromec
4918032 Method for fabricating three-dimensional microstructures and a high-sensitivity integrated vibra April 17, 1990
A method for preferentially etching phosphosilicate glass to form a micromechanical structure includes forming a layer of phosphosilicate glass on a substrate and opening at least one via in the phosphosilicate glass layer. A layer of material which is patterned to produce a micromec
4811063 JMOS transistor utilizing polysilicon sinks March 7, 1989
JMOS depletion mode transistors include back-to-back junctions in the doped polysilicon layer that serves as the gate. The polysilicon layer includes a first region of the same conductivity type as the channel in contact with the channel, and a second region, of the same conductivity typ
4800170 Process for forming in a silicon oxide layer a portion with vertical side walls January 24, 1989
A process for forming a buried patterned silicon oxide layer in a silicon chip in which the layer is formed by implanting oxygen into the chip through a mask of silicon oxide on the surface of the silicon chip. The silicon oxide mask is formed to have essentially vertical side walls by
4786952 High voltage depletion mode MOS power field effect transistor November 22, 1988
A vertical depletion mode power field effect transistor having a greatly increased drain-to-source breakdown voltage. The drain region is formed in the substrate and separated from the channel by a first insulative layer having apertures which allow the passage of electrical currents. Th
4746960 Vertical depletion-mode j-MOSFET May 24, 1988
A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interfa
4652334 Method for patterning silicon dioxide with high resolution in three dimensions March 24, 1987
A method is provided for selectively etching ion-implanted silicon dioxide. A masked silicon dioxide layer is exposed to an ion beam of controlled dose and energy. The mask is removed and the silicon dioxide layer is brought in contact with an aqueous ammoniacal hydrogen peroxide solutio










 
 
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