| Patent Number |
Title Of Patent |
Date Issued |
| 8253205 |
Method for forming strained channel PMOS devices and integrated circuits therefrom |
August 28, 2012 |
| An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region |
| 8252609 |
Curvature reduction for semiconductor wafers |
August 28, 2012 |
| A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semicondu |
| 8216945 |
Wafer planarity control between pattern levels |
July 10, 2012 |
| A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At leas |
| 8125035 |
CMOS fabrication process |
February 28, 2012 |
| Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional |
| 8124511 |
Method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disord |
February 28, 2012 |
| One aspect provides a method of manufacturing a semiconductor device having reduced N/P or P/N junction crystal disorder. In one aspect, this improvement is achieved by forming gate electrodes over a semiconductor substrate, amorphizing the semiconductor substrate that creates amorphous |
| 8026135 |
Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion |
September 27, 2011 |
| A process for forming diffused region less than 20 nanometers deep with an average doping dose above 10.sup.14 cm.sup.-2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GC |
| 7932139 |
Methodology of improving the manufacturability of laser anneal |
April 26, 2011 |
| A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam in a x-axis first direction, (b) moving the workpiece in a y-axis second direction, (c) moving the workpiece through a laser |
| 7902032 |
Method for forming strained channel PMOS devices and integrated circuits therefrom |
March 8, 2011 |
| An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region |
| 7883573 |
Method for preparing a source material for ion implantation |
February 8, 2011 |
| The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source |
| 7825025 |
Method and system for improved nickel silicide |
November 2, 2010 |
| According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanti |
| 7795122 |
Antimony ion implantation for semiconductor components |
September 14, 2010 |
| A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activatio |
| 7691714 |
Semiconductor device having a dislocation loop located within a boundary created by source/drain |
April 6, 2010 |
| The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and form |
| 7678637 |
CMOS fabrication process |
March 16, 2010 |
| Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional |
| 7670917 |
Semiconductor device made by using a laser anneal to incorporate stress into a channel region |
March 2, 2010 |
| In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted |
| 7666748 |
Method of forming amorphous source/drain extensions |
February 23, 2010 |
| A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing amorphous silicon within the recess to from amorphous silicon source/drain extensions. Dopants may be implanted into the amorphous |
| 7615458 |
Activation of CMOS source/drain extensions by ultra-high temperature anneals |
November 10, 2009 |
| A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remainin |
| 7557022 |
Implantation of carbon and/or fluorine in NMOS fabrication |
July 7, 2009 |
| Formation of an NMOS transistor is disclosed, where at least one of carbon, atomic fluorine and molecular fluorine (F.sub.2) are combined with implantations of at least one of arsenic, phosphorous and antimony. The dopant combinations can be used in LDD implantations to form source/d |
| 7557021 |
Highly doped gate electrode made by rapidly melting and resolidifying the gate electrode |
July 7, 2009 |
| The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also |
| 7511350 |
Nickel alloy silicide including indium and a method of manufacture therefor |
March 31, 2009 |
| The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a |
| 7494905 |
Method for preparing a source material including forming a paste for ion implantation |
February 24, 2009 |
| The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source |
| 7479668 |
Source/drain extension implant process for use with short time anneals |
January 20, 2009 |
| The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain exte |
| 7371648 |
Method for manufacturing a transistor device having an improved breakdown voltage and a method f |
May 13, 2008 |
| The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting |
| 7355255 |
Nickel silicide including indium and a method of manufacture therefor |
April 8, 2008 |
| The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) l |
| 7345355 |
Complementary junction-narrowing implants for ultra-shallow junctions |
March 18, 2008 |
| Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limit |
| 7344985 |
Nickel alloy silicide including indium and a method of manufacture therefor |
March 18, 2008 |
| The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a |
| 7344929 |
Method for manufacturing an integrated circuit using a capping layer having a degree of reflecti |
March 18, 2008 |
| The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having sour |
| 7306995 |
Reduced hydrogen sidewall spacer oxide |
December 11, 2007 |
| An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen con |
| 7297605 |
Source/drain extension implant process for use with short time anneals |
November 20, 2007 |
| The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (100). The process includes forming a gate (120) on a substrate (105) and forming a source/drain extension (160) in the substrate (105). Forming the source/drain exte |
| 7247535 |
Source/drain extensions having highly activated and extremely abrupt junctions |
July 24, 2007 |
| A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and |
| 7211516 |
Nickel silicide including indium and a method of manufacture therefor |
May 1, 2007 |
| The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) l |
| 7173296 |
Reduced hydrogen sidewall spacer oxide |
February 6, 2007 |
| An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen con |
| 7163878 |
Ultra-shallow arsenic junction formation in silicon germanium |
January 16, 2007 |
| In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium la |
| 7118980 |
Solid phase epitaxy recrystallization by laser annealing |
October 10, 2006 |
| Methods (70) are described for fabricating shallow and abrupt gradient drain extensions for MOS type transistors, in which a solid phase epitaxial recrystallization is performed within the drain extensions utilizing a laser SPER annealing process in the manufacture of semiconductor p |
| 7026218 |
Use of indium to define work function of p-type doped polysilicon |
April 11, 2006 |
| The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can |
| 6847089 |
Gate edge diode leakage reduction |
January 25, 2005 |
| An embodiment of the invention is an integrated circuit 2 having halo atoms 12 concentrated at a gate side of a channel region and impurity atoms 14 within the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implant |
| 6812073 |
Source drain and extension dopant concentration |
November 2, 2004 |
| A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gat |
| 6808997 |
Complementary junction-narrowing implants for ultra-shallow junctions |
October 26, 2004 |
| Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limit |
| 6803611 |
Use of indium to define work function of p-type doped polysilicon |
October 12, 2004 |
| The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can d |
| 6677201 |
Method of fabricating thermal CVD oxynitride and BTBAS nitride sidewall spacer for metal oxide s |
January 13, 2004 |
| A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed |
