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Jacquet; Francois
Froges, FR
No. of patents:

Patent Number Title Of Patent Date Issued
7872894 SRAM memory cell protected against current or voltage spikes January 18, 2011
A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state follo
7755927 Memory device of SRAM type July 13, 2010
A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the
7751229 SRAM memory device with improved write operation and method thereof July 6, 2010
A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simu
7741877 Circuit for distributing an initial signal with a tree structure, protected against logic random June 22, 2010
An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the
7688669 Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages March 30, 2010
A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is se
7623405 SRAM with switchable power supply sets of voltages November 24, 2009
A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependen
7623400 Memory device with programmable control for activation of read amplifiers November 24, 2009
An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory pl
7569889 Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fa August 4, 2009
A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high
7542333 Logic cell protected against random events June 2, 2009
A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and sec
7535743 SRAM memory cell protected against current or voltage spikes May 19, 2009
A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state follo
7447074 Read-only memory November 4, 2008
An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one,
7327594 Read-only memory with twisted bit lines February 5, 2008
Bit lines (BL0, BL0R, BL1, BL1R, . . . ) of a ROM memory array with differential detection reading are arranged within two overlaid metallization levels so as to increase the read reliability of binary values stored in the array. The ROM array is divided into matrix segments (100, 10
7321506 Multivibrator protected against current or voltage spikes January 22, 2008
The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, an
7272775 Memory circuit comprising an error correcting code September 18, 2007
A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first addr
7236031 Fast bistable circuit protected against random events June 26, 2007
A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive
7233512 Content addressable memory circuit with improved memory cell stability June 19, 2007
A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal node
7221581 Memory with storage cells biased in groups May 22, 2007
A memory circuit includes a plurality of storage cells (100) arranged in rows and columns thus forming a storage matrix. The storage cells (100) corresponding to the same bit line (21-23) are divided into several groups (60-61) of cells for the same column, these groups having their
7202518 Integrated dynamic random access memory element, array and process for fabricating such elements April 10, 2007
An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend between the source and drain
7184299 Nonvolatile SRAM memory cell February 27, 2007
An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18', 20') connected in series between a DC voltage supply source and a grounding circuit (22). A ci
7109541 Integrated circuit component, protected against random logic events, and associated method of ma September 19, 2006
A component of an integrated circuit comprises a first capacitor and a second capacitor series-connected between a first node and a second node of the component. This has application to logic circuits and bistable circuits, for example, SRAM type memories, flip-flop trigger circuits,
7057955 Dynamically unbalanced sense amplifier June 6, 2006
A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of th

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