| Patent Number |
Title Of Patent |
Date Issued |
| 7519928 |
Method for propagating phase constants in static model analysis of circuits |
April 14, 2009 |
| A method for propagating phase constants for static circuit model analysis is provided. The mechanisms of the illustrative embodiments make use of multiple phases of constant propagation to handle sequential elements in a circuit model. The phases are determined based on an oscillating c |
| 7490305 |
Method for driving values to DC adjusted/untimed nets to identify timing problems |
February 10, 2009 |
| A method for driving values to "don't care" (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in whi |
| 7484196 |
Method for asynchronous clock modeling in an integrated circuit simulation |
January 27, 2009 |
| Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or mor |
| 7484192 |
Method for modeling metastability decay through latches in an integrated circuit model |
January 27, 2009 |
| Mechanisms for modeling metastability decay through latches in an integrated circuit model are provided. Asynchronous clock boundaries are identified in the integrated circuit model and latches in a receive clock domain are enumerated. Latches within a range of the asynchronous clock |
| 7453759 |
Clock-gated model transformation for asynchronous testing of logic targeted for free-running, da |
November 18, 2008 |
| Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line |
| 7448015 |
Method and system for unfolding/replicating logic paths to facilitate modeling of metastable val |
November 4, 2008 |
| A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combinational logic and |
| 7447620 |
Modeling asynchronous behavior from primary inputs and latches |
November 4, 2008 |
| Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random |
| 7302659 |
System and method for unfolding/replicating logic paths to facilitate propagation delay modeling |
November 27, 2007 |
| A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently |
| 7299436 |
System and method for accurately modeling an asynchronous interface using expanded logic element |
November 20, 2007 |
| A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanism |
