| Patent Number |
Title Of Patent |
Date Issued |
| 7498219 |
Methods for reducing capacitor dielectric absorption and voltage coefficient |
March 3, 2009 |
| Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor. |
| 7396722 |
Memory device with reduced cell area |
July 8, 2008 |
| The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second act |
| 7344947 |
Methods of performance improvement of HVMOS devices |
March 18, 2008 |
| Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regi |
| 7045418 |
Semiconductor device including a dielectric layer having a gettering material located therein an |
May 16, 2006 |
| The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wher |
| 7019356 |
Memory device with reduced cell area |
March 28, 2006 |
| The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second act |
