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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Islam; Shafidul
Address:
Plano, TX
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
8058104 Reversible leadless package and methods of making and using same November 15, 2011
A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the se
8053869 Package having exposed integrated circuit device November 8, 2011
A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (2
7820480 Lead frame routed chip pads for semiconductor packages October 26, 2010
A redistributed lead frame for use in a molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of l
7795710 Lead frame routed chip pads for semiconductor packages September 14, 2010
A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands
7709935 Reversible leadless package and methods of making and using same May 4, 2010
A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package
7622332 Partially patterned lead frames and methods of making and using the same in semiconductor packag November 24, 2009
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on
7563648 Semiconductor device package and method for manufacturing same July 21, 2009
A lead frame (52, 100, 112) for a semiconductor device (die) package (50, 102, 110) is described. Each of the leads (60) in the lead frame (52, 100, 112) includes an interposer (64) having one end (66) disposed proximate the outer face (58) of the package (50, 102, 110) and another e
7554180 Package having exposed integrated circuit device June 30, 2009
A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing backside surface (14). A dielectric molding resin (26) at least partially encapsulates the integrated circuit die and the plurality of electrically conductive leads (2
7439097 Taped lead frames and methods of making and using the same in semiconductor packaging October 21, 2008
The invention provides a taped lead frame for use in manufacturing electronic packages. The taped lead frame is composed of a tape and a lead frame formed from a plurality of individual metal features attached to the tape and arranged in a footprint pattern. The method of making the
7262491 Die pad for semiconductor packages and methods of making and using same August 28, 2007
A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pa
7129116 Partially patterned lead frames and methods of making and using the same in semiconductor packag October 31, 2006
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on
6812552 Partially patterned lead frames and methods of making and using the same in semiconductor packag November 2, 2004
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on
6777265 Partially patterned lead frames and methods of making and using the same in semiconductor packag August 17, 2004
A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on
4812114 New IC molding process March 14, 1989
A molding system and process is disclosed to interface with existing wire bonders using a single track design from the bonder through the molding process. During the molding operation, the bonded lead frame is transferred into the mold on a guide track system built into the mold chas










 
 
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