| Patent Number |
Title Of Patent |
Date Issued |
| 7554163 |
Semiconductor device |
June 30, 2009 |
| A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region. |
| 7542368 |
Semiconductor memory device |
June 2, 2009 |
| A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors 108 and 111 included in a latch section is different from at least one of a potential supplied to a word line 105 and a potential supplied |
| 7495948 |
Semiconductor memory |
February 24, 2009 |
| In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupl |
| 7489581 |
Semiconductor memory |
February 10, 2009 |
| A semiconductor memory includes a plurality of memory cells, each of which includes a first inverter connected to one of high-data retaining supply lines which constitute one of high-data retaining supply line pairs corresponding to the memory cell and a second inverter connected to the |
| 7114140 |
Semiconductor device, semiconductor device design method, semiconductor device design method rec |
September 26, 2006 |
| Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from |
| 6924187 |
Method of making a semiconductor device with dummy diffused layers |
August 2, 2005 |
| A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The s |
| 6869808 |
Method for evaluating property of integrated circuitry |
March 22, 2005 |
| There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually |
| 6838736 |
Semiconductor device having noise immunity |
January 4, 2005 |
| A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The s |
| 6611950 |
Semiconductor device, semiconductor device design method, semiconductor device design method rec |
August 26, 2003 |
| Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from |
| 6502226 |
Semiconductor device, semiconductor device design method, semiconductor device design method rec |
December 31, 2002 |
| Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from |
| 6502225 |
Semiconductor device, semiconductor device design method, semiconductor device design method rec |
December 31, 2002 |
| Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from |
| 6421816 |
Semiconductor device, semiconductor device design method, semiconductor device design method rec |
July 16, 2002 |
| Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from |
| 6219630 |
Apparatus and method for extracting circuit, system and method for generating information for si |
April 17, 2001 |
| A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes |
