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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ishii; Takatoshi
Address:
Sunnyvale, CA
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
RE43235 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display March 13, 2012
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buff
RE41967 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display November 30, 2010
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buff
8288966 Color display October 16, 2012
A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light
8179401 Reducing image artifacts in a color sequential display system May 15, 2012
Methods, systems, and apparatus, including computer program products, for reducing artifacts in a color sequential display system. A frame of a digital image is displayed by receiving frame data, determining dither patterns, applying the dither patterns to the data, and displaying the
6680738 Single-block virtual frame buffer translated to multiple physical blocks for multi-block display January 20, 2004
A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buff
6639603 Hardware portrait mode support October 28, 2003
A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a dual mapped display memory having a
6362834 Flat-panel display controller with improved dithering and frame rate control March 26, 2002
A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smoot
6317165 System and method for selective capture of video frames November 13, 2001
A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by
6288698 Apparatus and method for gray-scale and brightness display control September 11, 2001
Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled
6052312 Multiple-port ring buffer April 18, 2000
A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an inte
6034733 Timing and control for deinterlacing and enhancement of non-deterministically arriving interlace March 7, 2000
A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by
6008794 Flat-panel display controller with improved dithering and frame rate control December 28, 1999
A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smoot
5896322 Multiple-port ring buffer April 20, 1999
A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an inte
5392239 Burst-mode DRAM February 21, 1995
A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequen










 
 
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