| Patent Number |
Title Of Patent |
Date Issued |
| 7608879 |
Semiconductor device including a capacitance |
October 27, 2009 |
| It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper la |
| 7598570 |
Semiconductor device, SRAM and manufacturing method of semiconductor device |
October 6, 2009 |
| A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is |
| 7556997 |
Method of manufacturing semiconductor device having impurity region under isolation region |
July 7, 2009 |
| In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N.sup.+ block region <41> in an N.sup.+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a& |
| 7553741 |
Manufacturing method of semiconductor device |
June 30, 2009 |
| Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a sem |
| 7541644 |
Semiconductor device with effective heat-radiation |
June 2, 2009 |
| The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A ba |
| 7535062 |
Semiconductor device having SOI structure |
May 19, 2009 |
| A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in |
| 7504291 |
MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable |
March 17, 2009 |
| It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI |
| 7494883 |
Semiconductor device having a trench isolation and method of fabricating the same |
February 24, 2009 |
| The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a |
| 7494880 |
Method of manufacturing semiconductor device |
February 24, 2009 |
| An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film i |
| 7470582 |
Method of manufacturing semiconductor device having impurity region under isolation region |
December 30, 2008 |
| In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N.sup.+ block region <41> in an N.sup.+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a& |
| 7453135 |
Semiconductor device and method of manufacturing the same |
November 18, 2008 |
| Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of t |
| 7449749 |
Semiconductor device for limiting leakage current |
November 11, 2008 |
| Formed on an insulator (9) are an N.sup.- type semiconductor layer (10) having a partial isolator formed on its surface and a P.sup.- type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P.sup.+ type semiconductor layers are provi |
| 7402865 |
Semiconductor device including a contact connected to the body and method of manufacturing the s |
July 22, 2008 |
| A Schottky junction is formed at the connection between an SOI layer and a contact (namely, under an element isolation insulating film) without forming a P.sup.+ region with a high impurity concentration thereat. The surface of a body contact is provide with a barrier metal. A silicide i |
| 7391095 |
Semiconductor device |
June 24, 2008 |
| In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole o |
| 7382026 |
Semiconductor memory device and method of manufacturing the same |
June 3, 2008 |
| A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically con |
| 7358555 |
Semiconductor device |
April 15, 2008 |
| While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered.Decoupling capacitors DM1 and |
| 7352049 |
Semiconductor device and method of manufacturing the same |
April 1, 2008 |
| Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of |
| 7339238 |
Semiconductor device including a capacitance |
March 4, 2008 |
| It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper la |
| 7332793 |
Semiconductor device |
February 19, 2008 |
| A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a |
| 7332776 |
Semiconductor device |
February 19, 2008 |
| A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation p |
| 7321152 |
Thin-film transistor and method of fabricating the same |
January 22, 2008 |
| Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same.A drain (6), a channel (7) and a source |
| 7307318 |
Semiconductor device |
December 11, 2007 |
| A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation p |
| 7303950 |
Semiconductor device, method of manufacturing same and method of designing same |
December 4, 2007 |
| A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well |
| 7300847 |
MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable |
November 27, 2007 |
| It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI |
| 7297585 |
Method of manufacturing semiconductor device having impurity region under isolation region |
November 20, 2007 |
| In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N.sup.+ block region <41> in an N.sup.+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a& |
| 7271454 |
Semiconductor memory device and method of manufacturing the same |
September 18, 2007 |
| A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically con |
| 7256463 |
Semiconductor device having SOI structure including a load resistor of an sram memory cell |
August 14, 2007 |
| It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain |
| 7187040 |
Thin-film transistor and method of fabricating the same |
March 6, 2007 |
| Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source |
| 7183624 |
Semiconductor device |
February 27, 2007 |
| A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a |
| 7183167 |
Semiconductor device having a trench isolation and method of fabricating the same |
February 27, 2007 |
| The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a |
| 7173319 |
Semiconductor device and method of manufacturing the same |
February 6, 2007 |
| Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), re |
| 7112854 |
Thin-film transistor and method of fabricating the same |
September 26, 2006 |
| Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source |
| 7112835 |
Semiconductor device including a capacitance |
September 26, 2006 |
| It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper la |
| 7105389 |
Method of manufacturing semiconductor device having impurity region under isolation region |
September 12, 2006 |
| In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N.sup.+ block region <41> in an N.sup.+ block resist film <51< prevents a well region <11> located under the gate-directional extension region <41a& |
| 7078767 |
Semiconductor device for limiting leakage current |
July 18, 2006 |
| Formed on an insulator (9) are an N.sup.- type semiconductor layer (10) having a partial isolator formed on its surface and a P.sup.- type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P.sup.+ type semiconductor layers are provi |
| 7067881 |
Semiconductor device |
June 27, 2006 |
| A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has bee |
| 7053451 |
Semiconductor device having impurity region under isolation region |
May 30, 2006 |
| In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N.sup.+ block region <41> in an N.sup.+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a& |
| 7005705 |
MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable |
February 28, 2006 |
| It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI |
| 6975041 |
Semiconductor storage device having high soft-error immunity |
December 13, 2005 |
| A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS |
| 6958266 |
Semiconductor device, method of manufacturing same and method of designing same |
October 25, 2005 |
| A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well r |
| 6953979 |
Semiconductor device, method of manufacturing same and method of designing same |
October 11, 2005 |
| A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well r |
| 6914307 |
Semiconductor device and method of manufacturing the same |
July 5, 2005 |
| A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation |
| 6879002 |
Semiconductor device having an SOI substrate |
April 12, 2005 |
| A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embe |
| 6875663 |
Semiconductor device having a trench isolation and method of fabricating the same |
April 5, 2005 |
| The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a |
| 6869865 |
Method of manufacturing semiconductor device |
March 22, 2005 |
| Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 .mu.m is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the |
| 6864534 |
Semiconductor wafer |
March 8, 2005 |
| To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do |
| 6858918 |
Semiconductor device including a capacitance |
February 22, 2005 |
| It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer |
| 6798021 |
Transistor having a graded active layer and an SOI based capacitor |
September 28, 2004 |
| By ion implantation process, a P-type impurity for element isolation is implanted at an impurity concentration (P1) into a silicon layer (3) defined between the bottom surface of an element isolation insulating film (5a) and the upper surface of a BOX layer (2). Resulting from this i |
| 6794717 |
Semiconductor device and method of manufacturing the same |
September 21, 2004 |
| It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain |
| 6756692 |
Semiconductor storage device having high soft-error immunity |
June 29, 2004 |
| A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors are driver transistors, NMOS transistors are access transistors, and PMOS transistors are load transistors. An NMOS transistor is a transistor |
