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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ikuta; Teruhisa
Address:
Nara, JP
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
8093131 Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and January 10, 2012
In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5,
7973361 High breakdown voltage semiconductor device and fabrication method of the same July 5, 2011
A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the activ
7944022 Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and May 17, 2011
In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5,
7719086 Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and May 18, 2010
In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5,
7485972 Semiconductor device February 3, 2009
Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad.
7342283 Semiconductor device March 11, 2008
An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed
7323747 Lateral semiconductor device January 29, 2008
In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P.sup.+-type source region (8), an N-type body region (4) and an N.sup.+-body contact diffusion region (10) are surrounded by a P.sup.+-type drain region (9) and a P-type drift region (5).
6989566 High-voltage semiconductor device including a floating block January 24, 2006
A high-voltage semiconductor device includes: a semiconductor region; a doped contact region; an isolating region; a metal electrode which is electrically connected with the doped contact region; and floating plate electrodes. A section of the metal electrode is extended onto an inte
6750506 High-voltage semiconductor device June 15, 2004
A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor regionm. Parts of the metal electrodes are extended onto the i










 
 
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