Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ichimura; Teruhiko
Address:
Kanagawa, JP
No. of patents:
2
Patents:












Patent Number Title Of Patent Date Issued
7163895 Polishing method January 16, 2007
The present invention is relates to a polishing method for polishing a semiconductor wafer (W) by pressing the semiconductor wafer (W) against a polishing surface (10) with use of a top ring (23) for holding the semiconductor wafer (W). A pressure chamber (70) is defined in the top r
5496749 Method of manufacturing thin film transistors in a liquid crystal display apparatus March 5, 1996
A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when










 
 
  Recently Added Patents
Semiconductor device with hetero-junction bodies
Fluid-borne particle detector
Liquid dispensing apparatus
Hydrogenolysis of ethyl acetate in alcohol separation processes
Image forming apparatus assembled with a fixing member and a pressing member
System, apparatus, and method for fast startup of USB devices
Triazolylphenyl sulfonamides as serine/threonine kinase inhibitors
  Randomly Featured Patents
Radio frequency transmitter having circuitry for regulating a mixing frequency adjusting output power, eliminating high frequency abnormalities, preventing audio/visual interference, and contr
Antiflammatory quinolin methoxy phenylsulphonamides
Match book
4-Alkyl-4-naphthyl butenes
System and method for measuring and utilizing pooling analytics
Method of manufacturing shaft unit
Methods of treating animals to maintain or enhance bone mineral content and compositions for use therein
Semiconductor device with lower capacitor electrode that includes islands of conductive oxide films arranged on a noble metal film
Process and apparatus for supplying air to a fuel cell system
Power supply pack structure