| Patent Number |
Title Of Patent |
Date Issued |
| 8278981 |
Low power variable delay circuit |
October 2, 2012 |
| A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input |
| 8189400 |
Data alignment circuit of semiconductor memory apparatus |
May 29, 2012 |
| A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in res |
| 8171189 |
Semiconductor apparatus |
May 1, 2012 |
| A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to |
| 8144531 |
Latency control circuit, semiconductor memory device including the same, and method for controll |
March 27, 2012 |
| A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a dela |
| 8144530 |
Semiconductor memory device and method for generating output enable signal |
March 27, 2012 |
| A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock s |
| 8143940 |
Internal supply voltage generating circuit and method for generating internal supply voltage |
March 27, 2012 |
| An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal su |
| 8120442 |
Semiconductor device |
February 21, 2012 |
| A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode |
| 8076964 |
Sampling circuit |
December 13, 2011 |
| A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with |
| 8035431 |
Delay locked loop and delay locking method having burst tracking scheme |
October 11, 2011 |
| A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase diff |
| 8026701 |
Voltage regulator for a synchronous clock system to reduce clock tree jitter |
September 27, 2011 |
| A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage gen |
| 7990785 |
Delay locked loop circuit of semiconductor device |
August 2, 2011 |
| A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clo |
| 7969214 |
DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit |
June 28, 2011 |
| A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and |
| 7936620 |
Receiver of semiconductor memory apparatus |
May 3, 2011 |
| A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the pre |
| 7884659 |
Phase mixer and delay locked loop including the same |
February 8, 2011 |
| A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value |
| 7868667 |
Output driving device |
January 11, 2011 |
| An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS |
| 7864605 |
Apparatus for removing crosstalk in semiconductor memory device |
January 4, 2011 |
| An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacen |
| 7847592 |
Buffer circuit of semiconductor memory apparatus |
December 7, 2010 |
| A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a vol |
| 7825699 |
Receiver circuit having compensated offset voltage |
November 2, 2010 |
| A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectiv |
| 7741888 |
PLL circuit having loop filter and method of driving the same |
June 22, 2010 |
| A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters t |
| 7667493 |
Data transmitter |
February 23, 2010 |
| Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output n |
| 7646223 |
Phase locked loop circuit having set initial locking level and control method thereof |
January 12, 2010 |
| A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase |
| 7642824 |
PLL circuit and method of controlling the same |
January 5, 2010 |
| A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a nois |
| 7629833 |
Power supply apparatus of semiconductor integrated circuit |
December 8, 2009 |
| A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance com |
