| Patent Number |
Title Of Patent |
Date Issued |
| 7968416 |
Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production |
June 28, 2011 |
| An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. |
| 7592648 |
Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production |
September 22, 2009 |
| An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. |
| 7038255 |
Integrated circuit arrangement having PNP and NPN bipolar transistors, and fabrication method |
May 2, 2006 |
| An explanation is given of, inter alia, an integrated circuit arrangement (100) containing an npn transistor (102) and a pnp transistor (104). Transistors with outstanding electrical properties are produced if the pnp transistor contains a cutout (142) for an edge terminal region (120) |
| 6958282 |
SOI semiconductor configuration and method of fabricating the same |
October 25, 2005 |
| A semiconductor configuration has a base layer made of semiconductor material and formed, in particular, by a substrate. An insulation layer is arranged above the base layer, and a layer made of monocrystalline silicon adjoins the insulation layer. A passivating substance is present, wit |
