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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hung; Kei-Kang
Address:
Changhua, TW
No. of patents:
6
Patents:












Patent Number Title Of Patent Date Issued
6894324 Silicon-on-insulator diodes and ESD protection circuits May 17, 2005
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region the
6861680 Silicon-on-insulator diodes and ESD protection circuits March 1, 2005
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region thereof
6747501 Dual-triggered electrostatic discharge protection circuit June 8, 2004
An integrated circuit that includes a signal pad, a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to
6653670 Silicon-on-insulator diodes and ESD protection circuits November 25, 2003
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, and which has more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region the
6649944 Silicon-on-insulator diodes and ESD protection circuits November 18, 2003
A silicon-on-insulator (SOI) gated diode and non-gated junction diode are provided. The SOI gated diode has a PN junction at the middle region under the gate, thus providing more junction area than a normal diode. The SOI non-gated junction diode has a PN junction at the middle region th
6639283 Semiconductor device with substrate-triggered ESD protection October 28, 2003
A semiconductor device with substrate-triggered ESD protection technique includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. The first MOS transistor array, the second MOS transistor array and the substrate-triggered p










 
 
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