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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hung; Chih-Wei
Address:
Hsin-Chu, TW
No. of patents:
40
Patents:












Patent Number Title Of Patent Date Issued
8300462 Single-transistor EEPROM array and operation methods October 30, 2012
A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-
8243527 Non-volatile field programmable gate array August 14, 2012
A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The
8120956 Single-transistor EEPROM array and operation methods February 21, 2012
An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of sourc
8000131 Non-volatile field programmable gate array August 16, 2011
A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The
7518912 Multi-level non-volatile memory April 14, 2009
A multi-level non-volatile memory including a memory cell disposed on a substrate is provided. The memory cell includes a control gate, a charge storage layer, a doped region, a select gate, and an assist gate. The control gate is disposed on the substrate. The charge storage layer is
7485529 Method of fabricating non-volatile memory February 3, 2009
A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substra
7436707 Flash memory cell structure and operating method thereof October 14, 2008
A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the st
7391073 Non-volatile memory structure and method of fabricating non-volatile memory June 24, 2008
A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of th
7262096 NAND flash memory cell row and manufacturing method thereof August 28, 2007
A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate
7196371 Flash memory March 27, 2007
A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings
7180128 Non-volatile memory, non-volatile memory array and manufacturing method thereof February 20, 2007
A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the sta
7166513 Manufacturing method a flash memory cell array January 23, 2007
A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a space
7061805 P-channel NAND flash memory and operating method thereof June 13, 2006
A p-channel NAND flash memory includes a plurality of memory cells in series connection between a p-type source region and a p-type drain region. Each memory cell includes a tunneling dielectric layer, a floating gate, and a control gate. An erase gate is formed between two adjacent
7057940 Flash memory cell, flash memory cell array and manufacturing method thereof June 6, 2006
A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a space
7029973 Method of fabricating a flash memory cell April 18, 2006
A method of forming a flash memory cell. A tunnel oxide layer, a floating gate layer, and a dielectric layer are formed on a substrate. A control gate layer is formed on the dielectric layer and then etched to form two control gates. The control gates are oxidized to form a plurality of
7005699 NAND flash memory cell row February 28, 2006
A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and
6963105 Flash memory cell structure November 8, 2005
A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacke
6917070 Single-poly EPROM and method for forming the same July 12, 2005
A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at
6914826 Flash memory structure and operating method thereof July 5, 2005
A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate s
6913974 Flash memory device structure and manufacturing method thereof July 5, 2005
A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the
6911690 Flash memory cell, flash memory cell array and manufacturing method thereof June 28, 2005
A flash memory cell array comprises a substrate, a string of memory cell structures and source region/drain region. Each of memory cell structures includes a stack gate structure including a select gate dielectric layer, a select gate and a gate cap layer formed on the substrate; a space
6875660 Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate el April 5, 2005
A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer.
6870212 Trench flash memory device and method of fabricating thereof March 22, 2005
A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate near the bottom of the trench, followed by forming
6855599 Fabrication method of a flash memory device February 15, 2005
A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source reg
6855598 Flash memory cell including two floating gates and an erasing gate February 15, 2005
A flash memory includes a substrate, at least a source and two drains formed in the substrate, and the source located between the drains, two tunnel oxide layers formed on the substrate between each drain and the source, a floating gate formed on each of the tunnel oxide layers, a pl
6838343 Flash memory with self-aligned split gate and methods for fabricating and for operating the same January 4, 2005
A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer
6834011 Structure, fabrication method and operating method for flash memory December 21, 2004
A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep
6791136 Memory device structure and method of fabricating the same September 14, 2004
A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a c
6778438 Structure, fabrication method and operating method for flash memory August 17, 2004
A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep
6774428 Flash memory structure and operating method thereof August 10, 2004
A flash memory structure is provided. The flash memory structure includes a P-type substrate, a deep N-well set up within the P-type substrate, a P-well set up within the deep N-well, a pair of gate structures set up over the substrate, a select gate set up between the pair of gate s
6770934 Flash memory device structure and manufacturing method thereof August 3, 2004
A flash memory device structure is provided. The flash memory device consists of a P-type substrate with an opening, a deep N-well region in the P-type substrate, a first gate structure and a second gate structure on the respective sidewalls of the opening, an insulating layer in the
6770925 Flush memory having source and drain edges in contact with the stacked gate structure August 3, 2004
A structure of a flash memory, having a deep P-well formed in an N-type substrate, an N-well formed in the deep P-well, a stacked gate structure formed on the substrate, an N-type source region and an N-type drain region formed in an N-well at two respective sides of the stacked gate,
6765260 Flash memory with self-aligned split gate and methods for fabricating and for operating the same July 20, 2004
A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer
6757208 Dual-bit nitride read only memory cell with parasitic amplifier and methods of fabricating and r June 29, 2004
Dual-bit nitride read only memory (NROM) cell with parasitic amplifier and method of fabricating and reading the same. A NROM cell comprises a semiconductor substrate with a first well region having a conductive type opposite that of the substrate disposed therein. A second well region
6730959 Structure of flash memory device and fabrication method thereof May 4, 2004
A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source reg
6696350 Method of fabricating memory device February 24, 2004
A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A mate
6653183 Single-poly EPROM and method for forming the same November 25, 2003
A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at
6642111 Memory device structure and method of fabricating the same November 4, 2003
A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a c
6639836 Method for reading flash memory with silicon-oxide/nitride/oxide-silicon (SONOS) structure October 28, 2003
A method for reading flash memory cell with SONOS structure is disclosed. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trap
6628550 Structure, fabrication and operation method of flash memory device September 30, 2003
A structure of a flash memory device. The flash memory comprises a deep n-well formed in a substrate, a p-well in the deep n-well, a stacked gate structure on the substrate, source and drain regions in the substrate at two respective sides of the stacked gate, an n-well extending from th










 
 
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