| Patent Number |
Title Of Patent |
Date Issued |
| 7572727 |
Semiconductor formation method that utilizes multiple etch stop layers |
August 11, 2009 |
| The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing |
| 7432178 |
Bit line implant |
October 7, 2008 |
| A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of |
| 7361587 |
Semiconductor contact and nitride spacer formation system and method |
April 22, 2008 |
| The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addr |
| 7341956 |
Disposable hard mask for forming bit lines |
March 11, 2008 |
| A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells. |
| 7323418 |
Etch-back process for capping a polymer memory device |
January 29, 2008 |
| The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides |
| 7301193 |
Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell |
November 27, 2007 |
| According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked |
| 7300886 |
Interlayer dielectric for charge loss improvement |
November 27, 2007 |
| A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control |
| 7285499 |
Polymer spacers for creating sub-lithographic spaces |
October 23, 2007 |
| A method includes forming a group of first structures on a semiconductor device and forming spacers adjacent side surfaces of each of the first structures to form a group of second structures. The method further includes using the group of second structures to form at least one sub-l |
| 7265014 |
Avoiding field oxide gouging in shallow trench isolation (STI) regions |
September 4, 2007 |
| A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond t |
| 7238571 |
Non-volatile memory device with increased reliability |
July 3, 2007 |
| A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer f |
| 7157335 |
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact r |
January 2, 2007 |
| The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of |
| 7115440 |
SO.sub.2 treatment of oxidized CuO for copper sulfide formation of memory element growth |
October 3, 2006 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or pla |
| 7018896 |
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEO |
March 28, 2006 |
| A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV |
| 7015135 |
Method and system for reducing contact defects using non conventional contact formation method f |
March 21, 2006 |
| A method and system for providing at least one contact in a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating layer on the interlayer dielectric, and at least one featur |
| 7015134 |
Method for reducing anti-reflective coating layer removal during removal of photoresist |
March 21, 2006 |
| A method and system for providing a semiconductor device. The semiconductor device includes a first layer to be etched. The method and system include depositing an anti-reflective coating. At least a portion of the anti-reflective coating layer is on the first layer. The method and s |
| 7012008 |
Dual spacer process for non-volatile memory devices |
March 14, 2006 |
| In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After imp |
| 6969654 |
Flash NVROM devices with UV charge immunity |
November 29, 2005 |
| A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent e |
| 6927129 |
Narrow wide spacer |
August 9, 2005 |
| A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comp |
| 6867097 |
Method of making a memory cell with polished insulator layer |
March 15, 2005 |
| An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering t |
| 6867063 |
Organic spin-on anti-reflective coating over inorganic anti-reflective coating |
March 15, 2005 |
| A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6808996 |
Method for protecting gate edges from charge gain/loss in semiconductor device |
October 26, 2004 |
| A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over |
| 6808992 |
Method and system for tailoring core and periphery cells in a nonvolatile memory |
October 26, 2004 |
| A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks hav |
| 6803267 |
Silicon containing material for patterning polymeric memory element |
October 12, 2004 |
| The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, a |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6774432 |
UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEO |
August 10, 2004 |
| A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opa |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6727143 |
Method and system for reducing charge gain and charge loss when using an ARC layer in interlayer |
April 27, 2004 |
| A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The method and system further include providing an antireflective |
| 6680507 |
Dual bit isolation scheme for flash memory devices having polysilicon floating gates |
January 20, 2004 |
| The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is prov |
| 6670265 |
Low K dielectic etch in high density plasma etcher |
December 30, 2003 |
| An integrated circuit wafer and a manufacturing process for etching low K spin-on dielectrics such as HSQ in a High Density Plasma etch reactor utilizes roof and wall temperature to improve across-the-wafer uniformity, and a mixture of C4F8 and C2F6 etch gases to eliminate mid via etch s |
| 6664191 |
Non self-aligned shallow trench isolation process with disposable space to define sub-lithograph |
December 16, 2003 |
| A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI reg |
| 6664180 |
Method of forming smaller trench line width using a spacer hard mask |
December 16, 2003 |
| An exemplary method of forming trench lines includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers |
| 6656763 |
Spin on polymers for organic memory devices |
December 2, 2003 |
| A method of making organic memory cells made of two electrodes with a controllably conductivce media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer and passive layer. The organic semiconductor layer is formed using spin- |
| 6653190 |
Flash memory with controlled wordline width |
November 25, 2003 |
| A method of manufacturing for a MirrorBit.RTM. Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric mate |
| 6635943 |
Method and system for reducing charge gain and charge loss in interlayer dielectric formation |
October 21, 2003 |
| A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using on |
| 6617215 |
Memory wordline hard mask |
September 9, 2003 |
| A manufacturing method for a MirrorBit.RTM. Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline |
| 6593632 |
Interconnect methodology employing a low dielectric constant etch stop layer |
July 15, 2003 |
| The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 .ANG. and a dielectric constant of less than about 3.2, thereby providing |
| 6589841 |
Charge gain/charge loss junction leakage prevention for flash technology by using double isolati |
July 8, 2003 |
| An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over |
| 6583009 |
Innovative narrow gate formation for floating gate flash technology |
June 24, 2003 |
| The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further compri |
| 6548334 |
Capping layer |
April 15, 2003 |
| A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer |
| 6528398 |
Thinning of trench and line or contact spacing by use of dual layer photoresist |
March 4, 2003 |
| An exemplary embodiment described in the disclosure relates to a method of fabricating an integrated circuit which includes providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging l |
| 6514874 |
Method of using controlled resist footing on silicon nitride substrate for smaller spacing of in |
February 4, 2003 |
| A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer |
| 6514868 |
Method of creating a smaller contact using hard mask |
February 4, 2003 |
| An exemplary method is described which forms a contact hole having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a contact hole is |
| 6514867 |
Method of creating narrow trench lines using hard mask |
February 4, 2003 |
| An exemplary method is described which forms narrow trench lines having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a trench line is |
| 6514849 |
Method of forming smaller contact size using a spacer hard mask |
February 4, 2003 |
| An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers |
| 6506683 |
In-situ process for fabricating a semiconductor device with integral removal of antireflection a |
January 14, 2003 |
| A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) is fabricated by performing a number of process steps in-situ. Semiconductor devices having local interconnect areas are formed on a surface of a semiconductor substrate. |
| 6501555 |
Optical technique to detect etch process termination |
December 31, 2002 |
| The disclosure describes an exemplary method of detecting a process end point during etching in the fabrication of an integrated circuit. This method can include receiving a reference signal indicative of an intensity of a light source, collecting a reflection signal reflected off a surf |
| 6479411 |
Method for forming high quality multiple thickness oxide using high temperature descum |
November 12, 2002 |
| A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least |
| 6479348 |
Method of making memory wordline hard mask extension |
November 12, 2002 |
| A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline mater |
| 6475867 |
Method of forming integrated circuit features by oxidation of titanium hard mask |
November 5, 2002 |
| An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first |
