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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hsueh; Cheng-Chen Calvin
Address:
Taipei, TW
No. of patents:
8
Patents:












Patent Number Title Of Patent Date Issued
6998316 Method for fabricating read only memory including a first and second exposures to a photoresist February 14, 2006
A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in th
6734064 Method for fabricating read only memory including forming masking layers with openings and pre-c May 11, 2004
A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in th
6670247 Method of fabricating mask read only memory December 30, 2003
A method of fabricating a mask read only memory. Embedded bit line are formed in a substrate. A gate dielectric layer and a word line are formed on the substrate. The word line is perpendicular to the bit lines. The substrate under the word line and between each pair of the bit lines is
6468897 Method of forming damascene structure October 22, 2002
A method of forming a damascene structure. A dielectric layer is formed over a substrate. The dielectric layer is a silicon oxynitride layer having a refractivity between 1.55 and 1.74. An opening is formed in the dielectric layer. A metallic layer that covers the substrate and compl
6448136 Method of manufacturing flash memory September 10, 2002
A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and
6444521 Method to improve nitride floating gate charge trapping for NROM flash memory device September 3, 2002
A method to improve nitride floating gate charge trapping for NROM flash memory device is disclosed. The present invention uses the SiON to replace the SiN of the NROM floating gate of the prior art. This arrangement improves the endurance and the reliability of the device and also exten
6136687 Method of forming air gaps for reducing interconnect capacitance October 24, 2000
A method for manufacturing integrated circuits increases the aspect ratio of the electrical conductor members connected to the circuits by increasing the effective height of the conductors, either by forming a thicker layer of conductor material prior to patterning the conductor memb
5981356 Isolation trenches with protected corners November 9, 1999
A method for forming trench isolation with spacers on the corners where the silicon and oxide intercept. A cavity is formed in silicon with a mask. Prior to completely removing the mask, the mask is further etched to enlarge the upper portion of the cavity. The cavity is filled with oxid










 
 
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