| Patent Number |
Title Of Patent |
Date Issued |
| 7425740 |
Method and structure for a 1T-RAM bit cell and macro |
September 16, 2008 |
| A one transistor (1T-RAM) bit cell and method for manufacture are provided. A metal-insulator-metal (MIM) capacitor structure and method of manufacturing it in an integrated process that includes a finFET transistor for the 1T-RAM bit cell is provided. In some embodiments, the finFET |
| 7400401 |
Measuring low dielectric constant film properties during processing |
July 15, 2008 |
| A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrome |
| 7378308 |
CMOS devices with improved gap-filling |
May 27, 2008 |
| A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device incl |
| 7341935 |
Alternative interconnect structure for semiconductor devices |
March 11, 2008 |
| A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etchi |
| 7316970 |
Method for forming high selectivity protection layer on semiconductor device |
January 8, 2008 |
| A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semico |
| 7271448 |
Multiple gate field effect transistor structure |
September 18, 2007 |
| A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel sp |
| 7265060 |
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates |
September 4, 2007 |
| An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb |
| 7259050 |
Semiconductor device and method of making the same |
August 21, 2007 |
| A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the |
| 7256498 |
Resistance-reduced semiconductor device and methods for fabricating the same |
August 14, 2007 |
| Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance- |
| 7256137 |
Method of forming contact plug on silicide structure |
August 14, 2007 |
| A method of manufacturing a semiconductor device is provided comprising the steps of: (a) forming a semiconductor element on a substrate, the semiconductor element having at least one nickel silicide contact region, a first etch stop layer formed over the element and an insulating layer |
| 7230270 |
Self-aligned double gate device and method for forming same |
June 12, 2007 |
| In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over |
| 7223647 |
Method for forming integrated advanced semiconductor device using sacrificial stress layer |
May 29, 2007 |
| An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS |
| 7179701 |
Transistor with high dielectric constant gate and method for forming the same |
February 20, 2007 |
| A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric |
| 7052946 |
Method for selectively stressing MOSFETs to improve charge carrier mobility |
May 30, 2006 |
| A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with |
| 7008878 |
Plasma treatment and etching process for ultra-thin dielectric films |
March 7, 2006 |
| A method for dry etching a dielectric layer including providing a substrate; forming at least one overlying dielectric layer over the substrate; subjecting the at least one overlying layer to a plasma oxidizing process; and, subjecting the at least one overlying layer to a plasma etc |
| 6884736 |
Method of forming contact plug on silicide structure |
April 26, 2005 |
| A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop l |
| 6838381 |
Methods for improving sheet resistance of silicide layer after removal of etch stop layer |
January 4, 2005 |
| A method of manufacturing a semiconductor device is provided. A nickel silicide layer (e.g., NiSi) is formed on a substrate. Next, a hydrogen plasma treatment may be performed on the silicide layer, which may induce the formation of metal/silicon hydride bonds in the silicide layer. An |
| 6787455 |
Bi-layer photoresist method for forming high resolution semiconductor features |
September 7, 2004 |
| A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containi |
| 6780782 |
Bi-level resist structure and fabrication method for contact holes on semiconductor substrates |
August 24, 2004 |
| An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique comb |
| 6706640 |
Metal silicide etch resistant plasma etch method |
March 16, 2004 |
| A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier |
| 6498067 |
Integrated approach for controlling top dielectric loss during spacer etching |
December 24, 2002 |
| A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during a |
