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Inventor:
Hsu; Chung
Address:
Cupertino, CA
No. of patents:
1
Patents:












Patent Number Title Of Patent Date Issued
4713329 Well mask for CMOS process December 15, 1987
A method of forming CMOS transistors with self-aligned field regions. First and second spaced apart areas are provided on a silicon substrate. A masking member is formed protecting the first of said areas and exposing the second. The exposed area is doped with a p-type material which is










 
 
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