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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hsu; Ching-Hsiang
Address:
Hsinchu, TW
No. of patents:
98
Patents:


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Patent Number Title Of Patent Date Issued
8232961 Pixel driving structure of displaying three colors of particle display and its displaying colors July 31, 2012
A pixel driving structure of a particle display displaying three colors and a method for displaying colors thereof are provided. The pixel driving structure includes a first substrate; a first electrode layer disposed on a surface of the first substrate; a second substrate disposed o
7960792 Non-volatile memory with a stable threshold voltage on SOI substrate June 14, 2011
A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a
7952934 Method for programming a memory structure May 31, 2011
A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure
7903472 Operating method of non-volatile memory March 8, 2011
An operating method of a non-volatile memory adapted for a non-volatile memory disposed on an SOI substrate including a first conductive type silicon body layer is provided. The non-volatile memory includes a gate, a charge storage structure, a second conductive type drain region, and a
7855918 Method for programming a memory structure December 21, 2010
A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure
7855417 Non-volatile memory with a stable threshold voltage on SOI substrate December 21, 2010
A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a
7724419 Display May 25, 2010
A display includes a first substrate, a first electrode, a second substrate, a second electrode and a display material layer. The first electrode is disposed on the first substrate and the second electrode is disposed on the second substrate. The display material layer is disposed be
7682908 Non-volatile memory and operating method thereof March 23, 2010
A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first dope
7551494 Single-poly non-volatile memory device and its operation method June 23, 2009
A single-poly, P-channel non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly, P-channel non-volatile memory cell includes an N well, a gate formed on the N well, a gate dielectric layer between the gate and
7447082 Method for operating single-poly non-volatile memory device November 4, 2008
A single-poly non-volatile memory cell that is fully compatible with nano-scale semiconductor manufacturing process is provided. The single-poly non-volatile memory cell includes an ion well, a gate formed on the ion well, a gate dielectric layer between the gate and the ion well, a
7433243 Operation method of non-volatile memory October 7, 2008
A non-volatile memory formed on a first conductive type substrate is provided. The non-volatile memory includes a gate, a second conductive type drain region, a charge storage layer, and a second conductive type first lightly doped region. The gate is formed on the first conductive t
7417897 Method for reading a single-poly single-transistor non-volatile memory cell August 26, 2008
A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cel
7262457 Non-volatile memory cell August 28, 2007
A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well
7250654 Non-volatile memory device July 31, 2007
A single-poly non-volatile memory device invented to integrate into logic process is disclosed. This non-volatile memory device includes a memory cell unit comprising a PMOS access transistor that is serially connected to a PMOS storage transistor formed in a cell array area, and, in a
7190623 Non-volatile memory cell and method of operating the same March 13, 2007
A memory cell includes an N-type well, three P-type doped regions formed on the N-type well, a dielectric layer formed on the N-type well and between a first doped region and a second doped region of the three P-type doped regions, a first gate formed on the dielectric layer, a charg
7172940 Method of fabricating an embedded non-volatile memory device February 6, 2007
A method of fabricating a non-volatile memory based on SONOS is disclosed. By masking the peripheral circuit area with a reverse ONO photoresist layer, the residual ONO layer that is not covered by a gate within the memory array area is etched away to expose the substrate. After the
6975545 Non-volatile memory cell December 13, 2005
A memory cell includes an N-type well, three P-type doped regions, a first stacked dielectric layer, a first gate, a second stacked dielectric layer, and a second gate. The three P-type doped regions are formed on the N-well. The first dielectric stack layer is formed on the N-type well
6952369 Method for operating a NAND-array memory module composed of P-type memory cells October 4, 2005
A method for writing a memory module includes providing a plurality of memory cells, applying a first transmission line voltage to the first transmission line of the column of a memory cell, turning on a P-type channel of a memory cell between the memory cell to be written and the fi
6924527 Split gate flash memory cell structure and method of manufacturing the same August 2, 2005
A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced
6922363 Method for operating a NOR-array memory module composed of P-type memory cells July 26, 2005
A method for writing a memory module includes providing a plurality of memory cells. Each memory cell includes a substrate, a P-type drain and source, a gate, and a stack dielectric layer which stores 2-bit data. Memory cells are arranged in a matrix with gates and sources on the same
6920067 Integrated circuit embedded with single-poly non-volatile memory July 19, 2005
A system on chip (SOC) contains a core circuit and an input/output (I/O) circuit embedded with an array of single-poly erasable programmable read only memory cells, each of which comprises a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS
6914825 Semiconductor memory device having improved data retention July 5, 2005
A NVM device encompasses a MOS select transistor including a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region. A MOS floating gate transistor is serially electrically connected to the
6908818 Contactless channel write/erase flash memory cell and its fabrication method June 21, 2005
A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N.sup.+ -doped region that acts as a drain of the flash memory cell and a
6888203 Power chip set for a switching mode power supply having a device for providing a drive signal to May 3, 2005
A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction
6888190 EEPROM with source line voltage stabilization mechanism May 3, 2005
A low-voltage nonvolatile memory array includes an N type semiconductor substrate having a memory region. A deep P well is formed in the semiconductor substrate. A cell N well is located within the memory region in the semiconductor substrate. The cell N well is situated above the deep
6885587 Single poly embedded EPROM April 26, 2005
A novel structure of nonvolatile memory is disclosed. The non-volatile memory includes two serially connected PMOS transistors. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted
6882574 Single poly UV-erasable programmable read only memory April 19, 2005
An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the
6847087 Bi-directional Fowler-Nordheim tunneling flash memory January 25, 2005
A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further
6842374 Method for operating N-channel electrically erasable programmable logic device January 11, 2005
An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second
6822286 Cmos-compatible read only memory and method for fabricating the same November 23, 2004
A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data "1" or digital data "0". The first and second single-poly PMOS transistors are both formed on a
6819594 Electrically erasable programmable logic device November 16, 2004
An electrically erasable programmable logic device includes a P-type substrate, a first N-type doped region located inside the P-type substrate, and a first gate located on the P-type substrate. The first gate is adjacent to the first N-type doped region, is in a floating state, and
6801456 Method for programming, erasing and reading a flash memory cell October 5, 2004
A method for programming PMOS single transistor flash memory cells through channel hot carrier induced hot electron injection mechanism is disclosed. The PMOS single transistor flash memory cell includes an ONO stack layer situated on an N-well of a semiconductor substrate, a P.sup.+ pol
6770950 Non-volatile semiconductor memory structure August 3, 2004
A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer
6750504 Low voltage single-poly flash memory cell and array June 15, 2004
A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, l
6740556 Method for forming EPROM with low leakage May 25, 2004
A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p.sup.+ doped region, a second p.sup.+ doped region, and a third p.sup.+ doped region on an N-well, forming a control gate between the first p.sup.+ doped region and the second p.sup.+ dope
6735115 Nonvolatile semiconductor memory device having divided bit lines May 11, 2004
A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by
6717206 Structure of an embedded channel write/erase flash memory cell and fabricating method thereof April 6, 2004
The present invention relates to a structure of an embedded channel write/erase flash memory cell and a fabricating method thereof and, more particularly, to a structure combining CMOS devices and flash memory cells, wherein flash memory cell structures and CMOS devices are simultane
6711064 Single-poly EEPROM March 23, 2004
A single-poly EEPROM is disxlosed. The single-poly EEPROM includes a first PMOS transistor that is serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P-type substrate. The first PMOS transistor includes a floating gate,
6710397 Nonvolatile semiconductor memory device having divided bit lines March 23, 2004
A non-volatile semiconuctor memory device having divided bit lines. A main bit line controlled by at least one bit line selection device to transfer its potential selected sub bit line, such that memory cells in a selected work and overloading of the bit line generated by a parasitic cap
6678190 Single poly embedded eprom January 13, 2004
An erasable programmable read only memory comprising two serially connected P-type metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode.
6677198 Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof January 13, 2004
The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a s
6654284 Channel write/erase flash memory cell and its manufacturing method November 25, 2003
A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and
6617637 Electrically erasable programmable logic device September 9, 2003
An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P.sup.+ dope
6580641 Method of forming and operating trench split gate non-volatile flash memory cell structure June 17, 2003
A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of
6573556 Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash June 3, 2003
A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source
6566703 High speed flash memory with high coupling ratio May 20, 2003
A flash memory device includes floating gate electrode, an interelectrode dielectric layer and a control gate electrode. The interelectrode dielectric layer is formed on top of the floating gate electrode and the control gate electrode is formed on top of the interelectrode dielectric
6534817 Contactless channel write/erase flash memory cell and its fabrication method March 18, 2003
A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N.sup.+ -doped region that acts as a drain of the flash memory cell and a
6518126 Method of forming and operating trench split gate non-volatile flash memory cell structure February 11, 2003
A method of forming and operating a trench split-gate non-volatile flash memory cell structure. The auxiliary gate of the structure is formed inside a trench on one side of the gate and the source terminal is underneath the auxiliary gate, thereby reducing overall area occupation of
6507066 Highly reliable flash memory structure with halo source January 14, 2003
A method of forming a Flash EEPROM device with a gate electrode stack includes forming a tunnel oxide layer, a floating gate electrode layer, a dielectric layer, and a control gate layer on a doped silicon semiconductor substrate. Then form source/drain regions in the substrate. Next
6504763 Nonvolatile semiconductor memory capable of random programming January 7, 2003
A nonvolatile semiconductor memory capable of random programming has a semiconductor substrate of a first conductivity type having a memory region, a deep ion well of a second conductivity type located in the semiconductor substrate within the memory region, a shallow ion well of the
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