Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hsieh; Chang-Ming
Address:
Fishkill, NY
No. of patents:
32
Patents:












Patent Number Title Of Patent Date Issued
6144081 Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structur November 7, 2000
A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across
6107141 Flash EEPROM August 22, 2000
An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly
5962895 SOI transistor having a self-aligned body contact October 5, 1999
SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes th
5910912 Flash EEPROM with dual-sidewall gate June 8, 1999
An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly
5729039 SOI transistor having a self-aligned body contact March 17, 1998
An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source.
5567553 Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structur October 22, 1996
A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across
5528062 High-density DRAM structure on soi June 18, 1996
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bi
5521399 Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit May 28, 1996
A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer i
5484738 Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits January 16, 1996
A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer i
5466625 Method of making a high-density DRAM structure on SOI November 14, 1995
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bi
5466625 Method of making a high-density DRAM structure on SOI November 14, 1995
A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bi
5446312 Vertical-gate CMOS compatible lateral bipolar transistor August 29, 1995
A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the coll
5405795 Method of forming a SOI transistor having a self-aligned body contact April 11, 1995
An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source.
5389559 Method of forming integrated interconnect for very high density DRAMs February 14, 1995
A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench
5385850 Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial January 31, 1995
A low temperature, epitaxial, in situ doped semiconductor layer is used as a sacrificial dopant source. The resulting doped region is small-dimensioned with a tightly controlled dopant concentration. The dopant layer is oxidized in a relatively low-temperature environment, and remove
5371022 Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor December 6, 1994
A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the coll
5366923 Bonded wafer structure having a buried insulation layer November 22, 1994
A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic ther
5341023 Novel vertical-gate CMOS compatible lateral bipolar transistor August 23, 1994
A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.
5340759 Method of making a vertical gate transistor with low temperature epitaxial channel August 23, 1994
A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., th
5315151 Transistor structure utilizing a deposited epitaxial base region May 24, 1994
A method of fabricating a semiconductor structure, comprising the steps of: providing a monocrystalline semiconductor device region of a first conductivity type; forming a layer of intrinsic monocrystalline semiconductor material over the device region; forming a layer of insulating
5313094 Thermal dissipation of integrated circuits using diamond paths May 17, 1994
A heat dissipation apparatus for dissipation of thermal energy from an isolated active silicon region to an underlying supportive substrate is disclosed. Such an apparatus comprises a diamond filled trench having walls extending through the isolated active silicon region, an underlying
5283456 Vertical gate transistor with low temperature epitaxial channel February 1, 1994
A field effect transistor (FET) with a vertical gate and a very thin channel sandwiched between source and drain layers. In a preferred embodiment of the invention, the FET is formed on a silicon on insulator (SOI) substrate with the silicon layer serving as the first layer (e.g., th
5276338 Bonded wafer structure having a buried insulation layer January 4, 1994
A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic ther
5258640 Gate controlled Schottky barrier diode November 2, 1993
An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.
5235206 Vertical bipolar transistor with recessed epitaxially grown intrinsic base region August 10, 1993
A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base
5202272 Field effect transistor formed with deep-submicron gate April 13, 1993
A method of forming a semiconductor structure comprising the steps of: providing a body of semiconductor material including at least one generally planar surface; forming a mesa having at least one generally vertical wall over the planar surface; forming a layer of material generally
5137840 Vertical bipolar transistor with recessed epitaxially grown intrinsic base region August 11, 1992
A method of manufacturing a vertical bipolar transistor including the steps of: providing a semiconductor substrate including a first region of a first conductivity type; forming an extrinsic base region of a second conductivity type in the surface of the first region, the extrinsic base
5045911 Lateral PNP transistor and method for forming same September 3, 1991
A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N
5043786 Lateral transistor and method of making same August 27, 1991
A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned port
4997775 Method for forming a complementary bipolar transistor structure including a self-aligned vertica March 5, 1991
A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a
4996164 Method for forming lateral PNP transistor February 26, 1991
A process of forming a lateral PNP transistor includes the steps of: providing a chip of semiconductor material including an isolated N- device region; implanting N dopant material at a relatively low power and low dosage into a selected implant region of the device region; implanting N
4965217 Method of making a lateral transistor October 23, 1990
A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned port










 
 
  Recently Added Patents
Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer
Asynchronous line interface rate adaptation to the physical layer with synchronous lines at the connection layer
Touch sensing technology
Catalyst compositions for hydroformylation reaction and hydroformylation process using the same
Mobile device mode control based on dual mapping of availability (presence) information
Method and apparatus for communication
Device and method for arranging vials
  Randomly Featured Patents
Devices for conveying and labelling containers and method for connecting a labelling unit to a conveyor unit
Extended range motor vehicle having ambient pollutant processing
Antenna system
Can removal method for use with a double action cupper
Marine anchor
Systems and methods for color defringing
Device for making bubbles in bath water
Ordering apparatus having walls with polygonal rotators
Method for chemically reducing metals in waste compositions
Organic pigments