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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Hopper; Peter J.
Address:
San Jose, CA
No. of patents:
195
Patents:


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Patent Number Title Of Patent Date Issued
8274129 Power transistor with improved high-side operating characteristics and reduced resistance and re September 25, 2012
A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes form
8212320 High voltage tolerant ESD device July 3, 2012
In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.
8130067 High frequency semiconductor transformer March 6, 2012
A semiconductor transformer provides high frequency operation by forming the primary windings of the transformer around a section of magnetic material that has a hard axis that lies substantially parallel to the direction of the magnetic field generated by the primary windings. The c
8098121 Method of switching a magnetic MEMS switch January 17, 2012
A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impuls
8081494 Fully integrated multi-phase grid-tie inverter December 20, 2011
In a grid-tie inverter, the DC input is phase and pulse-width modulated to define multiple phase shifted voltage pulses with the width of each pulse being modulated according to the grid AC amplitude for the corresponding portion of the AC phase.
8056246 Ferrofluidic orientation sensor and method of forming the sensor November 15, 2011
An orientation sensor includes a measure of ferrofluid that moves as the orientation sensor moves. The movement of the ferrofluid, which lies over a number of coils, alters the magnetic permeability of the flux path around each coil. The orientation sensor determines a change in orie
8042260 Methods of forming inductors on integrated circuits October 25, 2011
The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart
8004303 Method and system for measuring film stress in a wafer film August 23, 2011
In a MEMS wafer, film stresses are measured by placing an inductor array over or under the wafer and measuring inductance variations across the array to obtain a map defining the amount of bowing of the wafer.
8004061 Conductive trace with reduced RF impedance resulting from the skin effect August 23, 2011
The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms a
7978519 Method of reading an NVM cell that utilizes a gated diode July 12, 2011
A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel re
7973386 ESD protection bipolar device with internal avalanche diode July 5, 2011
In a bipolar device an intrinsic Zener like diode is formed for controlling the triggering voltage and leakage current, the Zener-like diode being formed between the n-collector and the p-base, wherein the collector implant and base diffusion overlap at least partially.
7969790 Method of erasing an NVM cell that utilizes a gated diode June 28, 2011
A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel
7968913 CMOS compatable fabrication of power GaN transistors on a <100> silicon substrate June 28, 2011
In an AlGaN channel transistor formed on a <100> orientation silicon wafer, a hole with walls slanted at 54 degrees is etched into the silicon to provide a <111> orientation substrate surface for forming the AlGaN channel transistor.
7936246 On-chip inductor for high current applications May 3, 2011
Saturation of nonlinear ferromagnetic core material for on-chip inductors for high current applications is significantly reduced by providing a core design wherein magnetic flux does not form a closed loop, but rather splits into multiple sub-fluxes that are directed to cancel each other
7935605 Lateral resurf NPN with high holding voltage for ESD applications May 3, 2011
In an ESD protection circuit an NPN BJT snapback device is provided with high breakdown voltage by including a RESURF region or by forming a PIN diode in the BJT. Holding voltage is increased by forming a sub-collector sinker region with the desired configuration.
7911869 Fuse-type memory cells based on irreversible snapback device March 22, 2011
In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
7910950 High voltage ESD LDMOS-SCR with gate reference voltage March 22, 2011
In an LDMOS-SCR ESD protection structure gate voltage of an ESD protection LDSCR is defined by connecting the gate to the source of a reference LDSCR. The reference LDSCR is implemented as a self-triggering device in which the snapback drain-source voltage (avalanche breakdown voltage) i
7897472 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integr March 1, 2011
Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlyi
7880261 Isolation technique allowing both very high and low voltage circuits to be fabricated on the sam February 1, 2011
An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isol
7875955 On-chip power inductor January 25, 2011
An on-chip inductor structure for a DC-DC power regulator circuit merges the switching transistor metallization with the inductor. Thick top level conductor metal that is used to strap the transistor array and to lower its on-state resistance is also used to extend the power inductor int
7872840 Erase pin protection in EEPROM using active snapback ESD device with positive feedback and shutd January 18, 2011
In an ESD protection circuit for an EEPROM erase pin a snapback device is provided for discharging high ESD currents, whereas the snapback device is operated in active mode during low voltage electrical overstress and to discharge post ESD event current by connecting an RC circuit over t
7859912 Mid-size NVM cell and array utilizing gated diode for low current programming December 28, 2010
A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also
7839242 Magnetic MEMS switching regulator November 23, 2010
A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impuls
7829425 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integr November 9, 2010
An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switch
7800127 ESD protection device with controllable triggering characteristics using driver circuit related September 21, 2010
In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided b
7796007 Transformer with signal immunity to external magnetic fields September 14, 2010
In an on-chip transformer, external electromagnetic field influences are reduced by providing an isolation transformer having primary and secondary windings with a figure 8 configuration so that current induced by an external magnetic field is nulled.
7795102 ESD high frequency diodes September 14, 2010
In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact t
7795047 Current balancing in NPN BJT and BSCR snapback devices September 14, 2010
In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to
7794510 On chip battery September 14, 2010
In an on chip battery and method of making an on-chip battery, the electrodes are formed from metal layers deposited as part of the chip fabrication process. An electrolyte is preferably introduced between the electrodes at time of packaging of the chip.
7764517 Power supply with reduced power consumption when a load is disconnected from the power supply July 27, 2010
Detection and control circuitry are added to a conventional power supply to detect when a load, such as a portable electronic device, has been disconnected from the power supply and, when disconnected, interrupt a current path to the primary windings of a transformer within the power
7755463 Integrated circuits with inductors July 13, 2010
The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also compr
7754986 Mechanical switch that reduces the effect of contact resistance July 13, 2010
A switch structure substantially reduces the effect of contact resistance by placing two mechanical switches in parallel between a source and a load, and sequentially closing and opening the mechanical switches so that one switch closes before the other switch, and opens after the other
7754540 Method of forming a SiGe DIAC ESD protection structure July 13, 2010
A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by
7754505 Method of forming a silicon-based light-emitting structure July 13, 2010
A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response
7718480 ESD clamps and NMOS arrays with increased electrical overstress robustness May 18, 2010
In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically
7714355 Method of controlling the breakdown voltage of BSCRs and BJT clamps May 11, 2010
In a BSCR or BJT ESD clamp, the breakdown voltage and DC voltage tolerance are controlled by controlling the size of the collector of the BJT device by masking part of the collector.
7705403 Programmable ESD protection structure April 27, 2010
In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as des
7701754 Multi-state electromechanical memory cell April 20, 2010
An electromechanical memory cell utilizes a cantilever and a laterally positioned electrode. The cantilever is spaced apart from the electrode by a distance that is greater than the elastic limit of the cantilever. The memory cell is programmed by applying voltages to the cantilever and
7676922 Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance March 16, 2010
A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a
7652348 Apparatus and method for wafer level fabrication of high value inductors on semiconductor integr January 26, 2010
An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry. Once the wa
7651913 Method of forming non-volatile memory (NVM) retention improvement utilizing protective electrica January 26, 2010
An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second po
7651897 Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing January 26, 2010
A method for manufacturing a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent
7642116 Method of forming a photodiode that reduces the effects of surface recombination sites January 5, 2010
The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination sites, and a seco
7639464 High holding voltage dual direction ESD clamp December 29, 2009
In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.
7635614 Double gate NLDMOS SCR device with controllable switching characteristics December 22, 2009
An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.
7602267 MEMS actuator and relay with horizontal actuation October 13, 2009
A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the
7598829 MEMS actuator and relay with vertical actuation October 6, 2009
A micro-electromechanical (MEMS) actuator and relay are implemented using a copper coil and a magnetic core. The magnetic core includes a base section that lies within the copper coil, and a cantilever section that lies outside of the copper coil. The presence of a magnetic field in the
7531824 High value inductor with conductor surrounded by high permeability polymer formed on a semicondu May 12, 2009
An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the
7528012 Method for forming heat sinks on silicon on insulator wafers May 5, 2009
An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat
7525323 Method for measuring permeability of a ferromagnetic material in an integrated circuit April 28, 2009
A method for determining consistency of a permeability of a ferromagnetic material in integrated circuits in which a test strip of the subject ferromagnetic material is included for testing with an impedance measurement instrument, such as an inductance-capacitance-resistance (LCR) m
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