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Honda; Takao
Tokyo, JP
No. of patents:

Patent Number Title Of Patent Date Issued
6119211 Circuit for controlling writing data into memory and allowing concurrent reset generation and wr September 12, 2000
There is provided a circuit for controlling writing data into an address of a memory, the data and address being transmitted from a central processing unit, the circuit (a) latching address and data transmitted from the central processing unit, (b) storing a first signal transmitted from

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